ROM_CTRL/32KB Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.970s 179.132us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.020s 1.852ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.430s 2.098ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.160s 166.031us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.130s 1.815ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.530s 179.127us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.430s 2.098ms 1 1 100.00
rom_ctrl_csr_aliasing 4.130s 1.815ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.070s 1.284ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.320s 123.912us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.310s 139.798us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 17.560s 578.933us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.920s 1.040ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.440s 919.512us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 5.430s 869.074us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 5.430s 869.074us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.020s 1.852ms 1 1 100.00
rom_ctrl_csr_rw 7.430s 2.098ms 1 1 100.00
rom_ctrl_csr_aliasing 4.130s 1.815ms 1 1 100.00
rom_ctrl_same_csr_outstanding 5.710s 546.491us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.020s 1.852ms 1 1 100.00
rom_ctrl_csr_rw 7.430s 2.098ms 1 1 100.00
rom_ctrl_csr_aliasing 4.130s 1.815ms 1 1 100.00
rom_ctrl_same_csr_outstanding 5.710s 546.491us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 40.350s 1.320ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 21.480s 8.669ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.488m 341.748us 1 1 100.00
rom_ctrl_tl_intg_err 37.790s 1.421ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.488m 341.748us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.488m 341.748us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 40.350s 1.320ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 40.350s 1.320ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 40.350s 1.320ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 40.350s 1.320ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 40.350s 1.320ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.488m 341.748us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.488m 341.748us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.970s 179.132us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.970s 179.132us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.970s 179.132us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 37.790s 1.421ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 40.350s 1.320ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.920s 1.040ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 40.350s 1.320ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 40.350s 1.320ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 40.350s 1.320ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 21.480s 8.669ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.488m 341.748us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.281m 32.063ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00