ROM_CTRL/64KB Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.650s 227.497us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.600s 550.917us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.870s 1.114ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 8.610s 701.258us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.560s 215.888us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.130s 868.645us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.870s 1.114ms 1 1 100.00
rom_ctrl_csr_aliasing 6.560s 215.888us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.150s 296.647us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.670s 728.912us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.030s 840.674us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 17.680s 594.185us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.680s 2.029ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.810s 553.737us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.250s 728.256us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.250s 728.256us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.600s 550.917us 1 1 100.00
rom_ctrl_csr_rw 6.870s 1.114ms 1 1 100.00
rom_ctrl_csr_aliasing 6.560s 215.888us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.950s 699.358us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.600s 550.917us 1 1 100.00
rom_ctrl_csr_rw 6.870s 1.114ms 1 1 100.00
rom_ctrl_csr_aliasing 6.560s 215.888us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.950s 699.358us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.602m 43.599ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 35.750s 2.700ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.519m 1.147ms 1 1 100.00
rom_ctrl_tl_intg_err 1.154m 388.356us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.519m 1.147ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.519m 1.147ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.602m 43.599ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.602m 43.599ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.602m 43.599ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.602m 43.599ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.602m 43.599ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.519m 1.147ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.519m 1.147ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.650s 227.497us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.650s 227.497us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.650s 227.497us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.154m 388.356us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.602m 43.599ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.680s 2.029ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.602m 43.599ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.602m 43.599ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.602m 43.599ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 35.750s 2.700ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.519m 1.147ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.184m 2.559ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00