RV_TIMER Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 1.520s 17.029us 1 1 100.00
V1 csr_hw_reset rv_timer_csr_hw_reset 1.900s 20.128us 1 1 100.00
V1 csr_rw rv_timer_csr_rw 1.500s 22.032us 1 1 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 2.200s 296.344us 1 1 100.00
V1 csr_aliasing rv_timer_csr_aliasing 1.620s 81.756us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 1.830s 67.984us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 1.500s 22.032us 1 1 100.00
rv_timer_csr_aliasing 1.620s 81.756us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 random_reset rv_timer_random_reset 6.840s 3.653ms 1 1 100.00
V2 disabled rv_timer_disabled 2.450s 697.342us 1 1 100.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 15.350m 2.482s 1 1 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 15.350m 2.482s 1 1 100.00
V2 stress rv_timer_stress_all 1.560s 118.605us 1 1 100.00
V2 alert_test rv_timer_alert_test 1.920s 13.450us 1 1 100.00
V2 intr_test rv_timer_intr_test 1.610s 26.619us 1 1 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 2.960s 1.348ms 1 1 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 2.960s 1.348ms 1 1 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 1.900s 20.128us 1 1 100.00
rv_timer_csr_rw 1.500s 22.032us 1 1 100.00
rv_timer_csr_aliasing 1.620s 81.756us 1 1 100.00
rv_timer_same_csr_outstanding 1.520s 77.487us 1 1 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 1.900s 20.128us 1 1 100.00
rv_timer_csr_rw 1.500s 22.032us 1 1 100.00
rv_timer_csr_aliasing 1.620s 81.756us 1 1 100.00
rv_timer_same_csr_outstanding 1.520s 77.487us 1 1 100.00
V2 TOTAL 8 8 100.00
V2S tl_intg_err rv_timer_sec_cm 1.960s 972.988us 1 1 100.00
rv_timer_tl_intg_err 2.550s 1.597ms 1 1 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 2.550s 1.597ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 min_value rv_timer_min 1.550s 34.042us 1 1 100.00
V3 max_value rv_timer_max 1.470s 11.519us 1 1 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 29.250s 9.778ms 1 1 100.00
V3 TOTAL 3 3 100.00
TOTAL 19 19 100.00