SPI_DEVICE/1R1W Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	28.810s	5.932ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.920s	14.021us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.550s	89.824us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	10.560s	711.168us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.930s	18.597ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.870s	153.537us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.550s	89.824us	1	1	100.00
		spi_device_csr_aliasing	16.930s	18.597ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.540s	36.125us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.580s	208.453us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.630s	23.342us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.460s	4.423us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.660s	7.126us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.650s	51.691us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.650s	51.691us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.770s	1.170ms	1	1	100.00
		spi_device_tpm_sts_read	1.630s	35.153us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	15.180s	27.320ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	7.750s	12.286ms	1	1	100.00
		spi_device_flash_all	16.780s	1.792ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.600s	109.578us	1	1	100.00
		spi_device_flash_all	16.780s	1.792ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.600s	109.578us	1	1	100.00
		spi_device_flash_all	16.780s	1.792ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	16.780s	1.792ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	7.330s	942.932us	1	1	100.00
		spi_device_flash_all	16.780s	1.792ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	7.330s	942.932us	1	1	100.00
		spi_device_flash_all	16.780s	1.792ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	7.330s	942.932us	1	1	100.00
		spi_device_flash_all	16.780s	1.792ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	7.330s	942.932us	1	1	100.00
		spi_device_flash_all	16.780s	1.792ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	7.330s	942.932us	1	1	100.00
		spi_device_flash_all	16.780s	1.792ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	7.650s	3.979ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	24.910s	5.890ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	24.910s	5.890ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	24.910s	5.890ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	5.810s	216.961us	1	1	100.00
		spi_device_read_buffer_direct	4.660s	2.518ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	24.910s	5.890ms	1	1	100.00
		spi_device_flash_all	16.780s	1.792ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	16.780s	1.792ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	16.780s	1.792ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.030s	200.019us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.030s	200.019us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	28.810s	5.932ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	29.950s	3.516ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.538m	386.203ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.630s	29.708us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.660s	12.214us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.870s	81.029us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.870s	81.029us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.920s	14.021us	1	1	100.00
		spi_device_csr_rw	2.550s	89.824us	1	1	100.00
		spi_device_csr_aliasing	16.930s	18.597ms	1	1	100.00
		spi_device_same_csr_outstanding	3.720s	80.684us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.920s	14.021us	1	1	100.00
		spi_device_csr_rw	2.550s	89.824us	1	1	100.00
		spi_device_csr_aliasing	16.930s	18.597ms	1	1	100.00
		spi_device_same_csr_outstanding	3.720s	80.684us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.110s	204.580us	1	1	100.00
		spi_device_tl_intg_err	14.170s	585.844us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	14.170s	585.844us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.297m	70.901ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.60562748474993029987035568310273664627049415788283434806836859661222415359616
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2830042 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[107])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2830042 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2830042 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1003])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.51787065559171466275473789894553273662210550877519100091742175700949807144941
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4297786 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7c25a2 [11111000010010110100010] vs 0x0 [0])
        UVM_ERROR @   4397786 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x74b489 [11101001011010010001001] vs 0x0 [0])
        UVM_ERROR @   4465786 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa86fa3 [101010000110111110100011] vs 0x0 [0])
        UVM_ERROR @   4518786 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb9b0b [10111001101100001011] vs 0x0 [0])
        UVM_ERROR @   4538786 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd1cddb [110100011100110111011011] vs 0x0 [0])