SPI_HOST Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	59.000s	4.221ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	18.092us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	26.571us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	309.822us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	24.625us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	36.709us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	26.571us	1	1	100.00
		spi_host_csr_aliasing	4.000s	24.625us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	13.922us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	18.713us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	3.000s	24.348us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	246.296us	1	1	100.00
		spi_host_error_cmd	4.000s	28.133us	1	1	100.00
		spi_host_event	18.000s	1.410ms	1	1	100.00
V2	clock_rate	spi_host_speed	4.000s	63.335us	1	1	100.00
V2	speed	spi_host_speed	4.000s	63.335us	1	1	100.00
V2	chip_select_timing	spi_host_speed	4.000s	63.335us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	30.000s	1.877ms	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	69.922us	1	1	100.00
V2	cpol_cpha	spi_host_speed	4.000s	63.335us	1	1	100.00
V2	full_cycle	spi_host_speed	4.000s	63.335us	1	1	100.00
V2	duplex	spi_host_smoke	59.000s	4.221ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	59.000s	4.221ms	1	1	100.00
V2	stress_all	spi_host_stress_all	7.000s	76.858us	1	1	100.00
V2	spien	spi_host_spien	5.000s	421.253us	1	1	100.00
V2	stall	spi_host_status_stall	2.733m	10.072ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	247.550us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	246.296us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	17.586us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	27.662us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	327.357us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	327.357us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	18.092us	1	1	100.00
		spi_host_csr_rw	4.000s	26.571us	1	1	100.00
		spi_host_csr_aliasing	4.000s	24.625us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	57.393us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	18.092us	1	1	100.00
		spi_host_csr_rw	4.000s	26.571us	1	1	100.00
		spi_host_csr_aliasing	4.000s	24.625us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	57.393us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	310.371us	1	1	100.00
		spi_host_sec_cm	4.000s	149.015us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	310.371us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	2.250m	14.065ms	1	1	100.00
		TOTAL			26	26	100.00