SRAM_CTRL/MAIN Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	7.790s	724.589us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.750s	28.117us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.520s	13.585us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.110s	52.653us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.580s	28.058us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.350s	356.851us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.520s	13.585us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	28.058us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.910m	18.758ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.547m	5.831ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	9.612m	17.382ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.388m	63.981ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	20.658m	81.616ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.661m	16.611ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	49.950s	19.204ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.561m	2.650ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	45.750s	10.370ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.584m	28.140ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	23.140s	821.390us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	9.770s	2.270ms	1	1	100.00
		sram_ctrl_throughput_w_readback	10.290s	2.976ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.207m	34.346ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.990s	365.600us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.076h	295.330ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.500s	13.776us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.620s	302.255us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.620s	302.255us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.750s	28.117us	1	1	100.00
		sram_ctrl_csr_rw	1.520s	13.585us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	28.058us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.730s	41.642us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.750s	28.117us	1	1	100.00
		sram_ctrl_csr_rw	1.520s	13.585us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	28.058us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.730s	41.642us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	35.260s	14.792ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.480s	1.054us	0	1	0.00
		sram_ctrl_tl_intg_err	3.040s	293.897us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.480s	1.054us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.040s	293.897us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.207m	34.346ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.207m	34.346ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.520s	13.585us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.561m	2.650ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.561m	2.650ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.561m	2.650ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	49.950s	19.204ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.470s	1.033ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	35.260s	14.792ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.200s	709.557us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	7.790s	724.589us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	7.790s	724.589us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.561m	2.650ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.480s	1.054us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	49.950s	19.204ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.480s	1.054us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.480s	1.054us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	7.790s	724.589us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.480s	1.054us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.142m	1.728ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.25472321682591346316491704821832663974723457284989325038464390909384335920473
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   1054168 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   1054168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---