SRAM_CTRL/RET Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	22.340s	418.623us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.610s	14.699us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.520s	52.557us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.760s	185.353us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.620s	14.573us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.930s	479.974us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.520s	52.557us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	14.573us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.540s	1.017ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.850s	353.259us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.347m	4.743ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.379m	5.951ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	50.270s	4.010ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.147m	12.519ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	9.800s	1.389ms	1	1	100.00
V2	executable	sram_ctrl_executable	1.041m	8.820ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	15.660s	4.383ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.506m	13.417ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	31.360s	108.261us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	5.220s	54.192us	1	1	100.00
		sram_ctrl_throughput_w_readback	33.850s	1.126ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.236m	9.580ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.120s	50.634us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	23.115m	20.391ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.720s	24.677us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.500s	75.161us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.500s	75.161us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.610s	14.699us	1	1	100.00
		sram_ctrl_csr_rw	1.520s	52.557us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	14.573us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.660s	38.601us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.610s	14.699us	1	1	100.00
		sram_ctrl_csr_rw	1.520s	52.557us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	14.573us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.660s	38.601us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.930s	708.237us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.710s	3.664us	0	1	0.00
		sram_ctrl_tl_intg_err	3.240s	217.252us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.710s	3.664us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.240s	217.252us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.236m	9.580ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.236m	9.580ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.520s	52.557us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.041m	8.820ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.041m	8.820ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.041m	8.820ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	9.800s	1.389ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.920s	122.206us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.930s	708.237us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.050s	105.893us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	22.340s	418.623us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	22.340s	418.623us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.041m	8.820ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.710s	3.664us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	9.800s	1.389ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.710s	3.664us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.710s	3.664us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	22.340s	418.623us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.710s	3.664us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.557m	1.741ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.30372232541755245805038668718662852550327183960544270412774042777372799006237
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3663976 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3663976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---