UART Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: cbe9098

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	3.590s	490.781us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.580s	19.431us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.620s	23.770us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.780s	169.317us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.710s	18.500us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.490s	105.168us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.620s	23.770us	1	1	100.00
		uart_csr_aliasing	1.710s	18.500us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	15.010s	51.362ms	1	1	100.00
V2	parity	uart_smoke	3.590s	490.781us	1	1	100.00
		uart_tx_rx	15.010s	51.362ms	1	1	100.00
V2	parity_error	uart_intr	3.640s	9.975ms	1	1	100.00
		uart_rx_parity_err	1.817m	117.866ms	1	1	100.00
V2	watermark	uart_tx_rx	15.010s	51.362ms	1	1	100.00
		uart_intr	3.640s	9.975ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.112m	93.001ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	10.190s	8.916ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	11.630s	37.414ms	1	1	100.00
V2	rx_frame_err	uart_intr	3.640s	9.975ms	1	1	100.00
V2	rx_break_err	uart_intr	3.640s	9.975ms	1	1	100.00
V2	rx_timeout	uart_intr	3.640s	9.975ms	1	1	100.00
V2	perf	uart_perf	8.672m	16.677ms	1	1	100.00
V2	sys_loopback	uart_loopback	4.090s	2.484ms	1	1	100.00
V2	line_loopback	uart_loopback	4.090s	2.484ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	12.840s	10.373ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.760s	3.754ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.450s	909.030us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	4.700s	2.963ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	7.820m	120.036ms	1	1	100.00
V2	stress_all	uart_stress_all	4.487m	87.149ms	1	1	100.00
V2	alert_test	uart_alert_test	1.430s	12.511us	1	1	100.00
V2	intr_test	uart_intr_test	1.640s	29.446us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.260s	75.380us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.260s	75.380us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.580s	19.431us	1	1	100.00
		uart_csr_rw	1.620s	23.770us	1	1	100.00
		uart_csr_aliasing	1.710s	18.500us	1	1	100.00
		uart_same_csr_outstanding	1.480s	40.747us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.580s	19.431us	1	1	100.00
		uart_csr_rw	1.620s	23.770us	1	1	100.00
		uart_csr_aliasing	1.710s	18.500us	1	1	100.00
		uart_same_csr_outstanding	1.480s	40.747us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.580s	42.621us	1	1	100.00
		uart_tl_intg_err	1.810s	520.103us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.810s	520.103us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	20.120s	3.015ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.102124532667569671682351458531974879862070679603326507504756456098423359419083
      Line 71, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 9916820743 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 9916831269 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 9916852321 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 95 [0x5f]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 10044753747 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 10044764273 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty