CHIP Simulation Results

Monday June 23 2025 17:05:19 UTC

GitHub Revision: `cbe9098`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	7.510m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	7.510m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	6.393m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	6.121m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	6.060m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.790m	5.669ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.790m	5.669ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.790m	5.669ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	27.110s	10.280us	0	1	0.00
		chip_sw_example_manufacturer	8.275m		0	1	0.00
		chip_sw_example_concurrency	3.795m	5.789ms	1	1	100.00
		chip_sw_uart_smoketest_signed	14.386s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.190s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.520s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.520s		0	1	0.00
V1	xbar_smoke	xbar_smoke	13.820s	12.251us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	7.505m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	11.893m	9.305ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.241m	3.323ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	5.886m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.592m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.058m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.882m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.550s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.550s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	7.417m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	7.390m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.631m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.631m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.026m	3.857ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.440m	3.093ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.756m	13.714ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.264s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.754s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	14.602m	26.830ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.825m	5.691ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.500m	18.015ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.500m	18.015ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	31.936s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.303m	4.738ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.303m	4.738ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.876m	18.017ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.324m	3.284ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.057m	5.006ms	1	1	100.00
		chip_sw_aes_idle	4.996m	5.092ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.254m	4.694ms	1	1	100.00
		chip_sw_kmac_idle	4.237m	4.012ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.897m	12.021ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.654m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	10.774m	12.020ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	10.992m	12.022ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	13.186s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.929s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.675s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.338s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.623s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.442s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.797s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	13.186s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.929s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.675s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.338s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.623s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.442s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.797s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	17.713s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.073m	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	34.280s	10.120us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.380s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.880s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.835s		0	1	0.00
		chip_sw_clkmgr_jitter	3.643m	3.668ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.793m	5.835ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.209s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	41.010s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	42.170s	10.380us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	33.710s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	34.440s	10.240us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	33.280s	10.260us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.705s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.054s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.637s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.006s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	18.398m	16.165ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.638m	14.137ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.303m	4.738ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.503s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.638m	14.137ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	34.987s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	33.470s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	15.708s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	15.580s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	21.634s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	18.398m	16.165ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.756m	13.714ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	20.947m	20.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	5.879m	7.549ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	7.243m	8.019ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.515m	4.803ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	18.398m	16.165ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	17.978s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.889s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	18.398m	16.165ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.338s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	7.243m	8.019ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	14.856s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.322s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.887s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.857s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.259s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	13.001s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.889s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	17.160s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	2.918m		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	17.160s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	17.160s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	17.160s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.399m	10.005ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.914m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	2.934m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	24.563s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	11.396s		0	1	0.00
		chip_sw_lc_ctrl_transition	17.160s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.284m	10.629ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.131m	13.512ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.213s		0	1	0.00
		chip_prim_tl_access	11.981m	19.771ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	13.186s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.929s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.675s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.338s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.623s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.442s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.797s		0	1	0.00
		chip_rv_dm_lc_disabled	14.602m	26.830ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.340m	4.888ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.073m	10.160us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.295m	3.517ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.996m	5.092ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.046m	3.124ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	34.280s	10.120us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.254m	4.694ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.379m	3.278ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.073m	4.159ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	36.880s	10.360us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.284m	10.629ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	17.160s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	33.030s	10.100us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.030m	4.033ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.237m	4.012ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.762s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.762s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.101s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.373m	4.312ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.856s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.284m	10.629ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.380s	10.140us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	11.941s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	17.713s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.057m	5.006ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.057m	5.006ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.057m	5.006ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.846m	6.353ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.131m	13.512ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.131m	13.512ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.330m	6.828ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.835s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.213s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	18.398m	16.165ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.631m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	17.160s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.846m	6.353ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.284m	10.629ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.330m	6.828ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.284m	3.501ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.846m	6.353ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.284m	10.629ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.330m	6.828ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.284m	3.501ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	17.160s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.676s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	2.918m		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.914m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	2.934m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	24.563s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	11.396s		0	1	0.00
		chip_sw_lc_ctrl_transition	17.160s		0	1	0.00
		chip_prim_tl_access	11.981m	19.771ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	11.981m	19.771ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	13.298s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	13.222s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.054s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	17.713s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.073m	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	34.280s	10.120us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	35.380s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.880s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.835s		0	1	0.00
		chip_sw_clkmgr_jitter	3.643m	3.668ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.647m	6.948ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.647m	6.948ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.668m	4.938ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	2.974m	3.600ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.044m	6.030ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.427m	5.106ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.918m	5.494ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.795m	5.259ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.284m	3.501ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	20.947m	20.018ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	20.947m	20.018ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.459m	4.805ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.543m	5.963ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.838m	3.597ms	1	1	100.00
		chip_sw_csrng_smoketest	3.583m	4.273ms	1	1	100.00
		chip_sw_gpio_smoketest	3.339m	4.977ms	1	1	100.00
		chip_sw_hmac_smoketest	4.397m	5.076ms	1	1	100.00
		chip_sw_kmac_smoketest	3.540m	4.263ms	1	1	100.00
		chip_sw_otbn_smoketest	4.456m	4.271ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.484m	5.096ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.326m	3.603ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.833m	5.294ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.384m	3.183ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.470m	4.009ms	1	1	100.00
		chip_sw_uart_smoketest	3.511m	3.920ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	14.502s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	14.386s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	7.505m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.525s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.508m	5.073ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.167m	3.949ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.108m	5.466ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.910m	3.953ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	25.054s		0	1	0.00
		chip_rv_dm_lc_disabled	14.602m	26.830ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	14.740s		0	1	0.00
		chip_sw_lc_walkthrough_prod	20.824s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	20.529s		0	1	0.00
		chip_sw_lc_walkthrough_rma	25.422s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	25.054s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	17.030s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	56.354s		0	1	0.00
		rom_volatile_raw_unlock	16.684s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.953s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	6.909m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	7.216m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.484m	3.598ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.484m	3.598ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.520s		0	1	0.00
		chip_same_csr_outstanding	8.730s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.520s		0	1	0.00
		chip_same_csr_outstanding	8.730s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	2.718m	503.888us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.240s	12.182us	1	1	100.00
		xbar_smoke_large_delays	4.399m	2.501ms	1	1	100.00
		xbar_smoke_slow_rsp	5.888m	2.446ms	1	1	100.00
		xbar_random_zero_delays	49.410s	49.003us	1	1	100.00
		xbar_random_large_delays	13.341m	7.484ms	1	1	100.00
		xbar_random_slow_rsp	26.993m	10.509ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	36.700s	25.560us	1	1	100.00
		xbar_error_and_unmapped_addr	50.180s	40.112us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.151m	429.593us	1	1	100.00
		xbar_error_and_unmapped_addr	50.180s	40.112us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	59.580s	67.158us	1	1	100.00
		xbar_access_same_device_slow_rsp			0	1	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	2.558m	477.323us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	5.036m	301.191us	1	1	100.00
		xbar_stress_all_with_error	7.574m	535.743us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	27.198m	1.041ms	1	1	100.00
		xbar_stress_all_with_reset_error	9.429m	365.096us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.641s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.694s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.540s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.898s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.092s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.935s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.460s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.356s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.408s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.436s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.589s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	13.108s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.302s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.700s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.167s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.971s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.744s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.426s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.761s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.902s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	14.074s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.356s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	14.558s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.201s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.739s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	13.109s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.797s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.050s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.075s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.559s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.966s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.337s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.728s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.455s		0	1	0.00
		rom_e2e_asm_init_dev	11.699s		0	1	0.00
		rom_e2e_asm_init_prod	11.701s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.978s		0	1	0.00
		rom_e2e_asm_init_rma	12.870s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.149s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.149s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.514s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.728s		0	1	0.00
V2		TOTAL			64	205	31.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.260m	4.722ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.320m	3.539ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.188s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.160s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.115s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.012s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	18.398m	16.165ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	18.624s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.899m	14.809ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.901s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.833s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.188s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.160s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.115s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.379s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.124s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.534s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.217m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	17.930m	12.569ms	1	1	100.00
		chip_plic_all_irqs_0	9.490m	6.022ms	1	1	100.00
		chip_plic_all_irqs_10	9.896m	6.318ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.140m	4.895ms	1	1	100.00
		chip_sw_dma_abort	4.370m	3.889ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.344s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.430s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.936s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.114s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.397s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.814s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.282s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.213s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.344s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.700s		0	1	0.00
		chip_sw_mbx_smoketest	4.264m	5.687ms	1	1	100.00
		TOTAL			75	247	30.36

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.91103070509682546295177474635945555315729653662326673886262522489852485153576
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (cbbe28)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 480.364s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.95512801139511693633331607703733391948687311884414478858551814542088667222569
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (7c818a)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 435.904s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.71093939009216532369656266641321151224504285699813100116085066577917270452219
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (83ffa5)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 434.320s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.34660278779224416420809098496261193328700424396486497165003158792312630858600
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b505ab)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 432.802s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.9413888005423270282350517832595845642419590058658460702388360765781856202622
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (c16296)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 439.257s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.49259576156157717842463843592026699435827577649042746325847782186018030231269
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.34692298485039988610584869397936243036255975153713241574257608165462255263357
    Line 419, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.65853526994219151138678042385948915002108876242953576425476229504944033209508
    Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.17211533982061426755590056646730130597970455134699214159817471009283151924753
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.11347045380648027358395240008182254559865936624233171369157582653768736964386
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.14934251678581388258824295218197935608402786375124366128348454767436558059987
Line 541, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.449809 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.449809 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.99394758830503521834467510820522102478736394065627444330349936929827038801817
Line 488, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18014.657654 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18014.657654 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.66318662851071562261909272058752503408162330074301909979616725557736457250245
Line 497, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18017.440806 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.440806 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.77879870679523868197946971716420576038153158837330836983694738107450303382211
Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12022.136066 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12022.136066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.73859972099640898509908998303712050902618147213742225983839441298529881043055
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.22602461551610421847995548692803267433904018305050377788627999388942053929537
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.59556247254112678289920029600755808577962349033318559782784399418120188070621
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.40195566710876564101550081320264852799442382621329449567312473082603034818199
Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12021.110486 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12021.110486 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.43379118862194932079445324788128897438472591360569941529131835138422165276942
Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12018.679190 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.679190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.93939306946538469641770268140553238103422345917468218417967628867419837740040
Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12020.150512 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12020.150512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.89371971808070863208753154079652009285085375142009031754406649761594150425844
Line 491, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 10628.620584 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (7256937813315445967599593780858139777815501750154263257606437735647810222288 [0x100b47ffb91a509bff42930360c61c37b2061e89c03a73c73536ed38d598f8d0] vs 18489970166030013777138776797340427634416364806708019901307425986886846582651 [0x28e0f3c6a89d94aa39fc72db6076f1adb26800d68a24d3d714a6fa7d66830f7b])
  UVM_INFO @ 10628.620584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.11018406810038853320311400939525191338280365492275671561858301758341742487956
Line 484, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 10005.235864 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (87234119113417154462412852505132798441501577521821796833535543266119073808692 [0xc0dcc2ffa721de9d63895e5d5467e3f92a1b2a119a26a2ec0dd5b23f4a824134] vs 72093778558115208728559508202176601163083223869110087771561417790874591903372 [0x9f63a1f48a635d941e48c7cfa0bb31d989fd989414e1dbb984a697b433773e8c])
  UVM_INFO @ 10005.235864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.29404181010823872679405830835496908684444846333982042283632686632808459054147
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3857.074351 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h28aef6ef  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h11  a_opcode: 'h1  a_user: 'h248c0  d_param: 'h0  d_source: 'h11  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3857.074351 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.99426086060151497072227586033341675983571726004902248091528515432594867499540
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3092.715747 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h97349431  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1f  a_opcode: 'h0  a_user: 'h2694a  d_param: 'h0  d_source: 'h1f  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3092.715747 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.10225883846994384337139644859955742896868857296395732154220368076650209615838
    Line 1044, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.3922569563013501065608694563044348295302660603637918889116573061701047215709
    Line 555, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3323.100472 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3323.100472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.106096710902073556563402365555949286368080814345480618781362411738159233875532
    Line 691, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 8019.224700 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 8019.224700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.2810229987411335101625108949228273995333407568722495851410271265346374239133
    Line 488, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4937.675888 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4937.675888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.59156878750389142939779479734030759721545798289454668451951995718968927384966
    Line 469, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3600.360296 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3600.360296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.19424797837870337613959361351942741446946801515886989244896440084878737864401
    Line 499, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4737.632216 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4737.632216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.97015667412857676265522579650149839577756199984194658561840415253609099393262
    Line 443, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5105.806676 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5105.806676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.96709055621835388243410896589469333069788141951803504526736969977415377627434
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.52846577031488470776112741536392828838032471842420610321462897164943020864735
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3597.868540 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3597.868540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.88262877964601975196918373309973391954879838312213802082975205738456711916896
    Line 401, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13714.201684 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13714.201684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.79918275184871622765521449000704321479589640070588618745112924680957074794185
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 96
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.84217445092445135173162785427692498656970751992424445309261730391849414078933
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3888.781360 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3888.781360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test xbar_access_same_device_slow_rsp has 1 failures.
  - 0.xbar_access_same_device_slow_rsp.17731303914265681934592107911683020162315957376080764570819503922776159753174
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```