DMA Simulation Results

Tuesday September 02 2025 21:26:11 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	1.100ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	1.406ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	6.000s	260.844us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	3.000s	16.586us	1	1	100.00
V1	csr_rw	dma_csr_rw	3.000s	57.913us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	12.000s	3.804ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	14.000s	3.340ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	3.000s	30.390us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	3.000s	57.913us	1	1	100.00
		dma_csr_aliasing	14.000s	3.340ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	32.000s	1.573ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	6.733m	132.039ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	3.967m	35.815ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	3.967m	35.815ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	6.733m	132.039ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	10.633m	55.472ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	3.967m	35.815ms	1	1	100.00
V2	dma_abort	dma_abort	11.000s	3.221ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	4.783m	50.010ms	1	1	100.00
V2	alert_test	dma_alert_test	3.000s	43.211us	1	1	100.00
V2	intr_test	dma_intr_test	3.000s	11.667us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	267.236us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	267.236us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	3.000s	16.586us	1	1	100.00
		dma_csr_rw	3.000s	57.913us	1	1	100.00
		dma_csr_aliasing	14.000s	3.340ms	1	1	100.00
		dma_same_csr_outstanding	4.000s	67.060us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	3.000s	16.586us	1	1	100.00
		dma_csr_rw	3.000s	57.913us	1	1	100.00
		dma_csr_aliasing	14.000s	3.340ms	1	1	100.00
		dma_same_csr_outstanding	4.000s	67.060us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	22.000s	74.858us	1	1	100.00
		dma_generic_stress	10.633m	55.472ms	1	1	100.00
		dma_handshake_stress	3.967m	35.815ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	8.000s	327.735us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	536.475us	1	1	100.00
		dma_sec_cm	3.000s	37.417us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	2.750m	9.109ms	1	1	100.00
		dma_longer_transfer	7.000s	753.003us	1	1	100.00
		dma_stress_all_with_rand_reset	12.000s	769.465us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:946) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.45816629622364346211307552335941300005445751997356093674589676264001780983346
      Line 100, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  769464944ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  769464944ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---