EDN Simulation Results

Tuesday September 02 2025 21:26:11 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.970s 48.911us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.010s 19.888us 1 1 100.00
V1 csr_rw edn_csr_rw 1.010s 17.935us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.540s 169.535us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.040s 19.039us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.220s 36.977us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.010s 17.935us 1 1 100.00
edn_csr_aliasing 1.040s 19.039us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.240s 65.355us 1 1 100.00
V2 csrng_commands edn_genbits 1.240s 65.355us 1 1 100.00
V2 genbits edn_genbits 1.240s 65.355us 1 1 100.00
V2 interrupts edn_intr 0.860s 37.454us 1 1 100.00
V2 alerts edn_alert 1.240s 25.497us 1 1 100.00
V2 errs edn_err 1.310s 30.854us 1 1 100.00
V2 disable edn_disable 0.870s 26.063us 1 1 100.00
edn_disable_auto_req_mode 1.010s 36.076us 1 1 100.00
V2 stress_all edn_stress_all 4.140s 275.138us 1 1 100.00
V2 intr_test edn_intr_test 0.970s 58.228us 1 1 100.00
V2 alert_test edn_alert_test 1.160s 21.475us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 1.760s 33.711us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 1.760s 33.711us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.010s 19.888us 1 1 100.00
edn_csr_rw 1.010s 17.935us 1 1 100.00
edn_csr_aliasing 1.040s 19.039us 1 1 100.00
edn_same_csr_outstanding 1.220s 45.951us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.010s 19.888us 1 1 100.00
edn_csr_rw 1.010s 17.935us 1 1 100.00
edn_csr_aliasing 1.040s 19.039us 1 1 100.00
edn_same_csr_outstanding 1.220s 45.951us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.660s 1.080ms 1 1 100.00
edn_tl_intg_err 1.380s 51.861us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.910s 85.833us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.240s 25.497us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.660s 1.080ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.660s 1.080ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.660s 1.080ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.660s 1.080ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.240s 25.497us 1 1 100.00
edn_sec_cm 6.660s 1.080ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.240s 25.497us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.380s 51.861us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets