ENTROPY_SRC/RNG_16BITS Simulation Results

Tuesday September 02 2025 21:26:11 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	entropy_src_smoke	4.000s	37.033us	1	1	100.00
V1	csr_hw_reset	entropy_src_csr_hw_reset	4.000s	63.196us	1	1	100.00
V1	csr_rw	entropy_src_csr_rw	3.000s	15.261us	1	1	100.00
V1	csr_bit_bash	entropy_src_csr_bit_bash	9.000s	152.330us	1	1	100.00
V1	csr_aliasing	entropy_src_csr_aliasing	6.000s	263.649us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	entropy_src_csr_mem_rw_with_rand_reset	4.000s	123.409us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	entropy_src_csr_rw	3.000s	15.261us	1	1	100.00
		entropy_src_csr_aliasing	6.000s	263.649us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	entropy_src_smoke	4.000s	37.033us	1	1	100.00
		entropy_src_rng	3.667m	18.137ms	1	1	100.00
		entropy_src_fw_ov	4.283m	9.031ms	1	1	100.00
V2	firmware_mode	entropy_src_fw_ov	4.283m	9.031ms	1	1	100.00
V2	rng_mode	entropy_src_rng	3.667m	18.137ms	1	1	100.00
V2	rng_max_rate	entropy_src_rng_max_rate	5.933m	9.046ms	1	1	100.00
V2	health_checks	entropy_src_rng	3.667m	18.137ms	1	1	100.00
V2	conditioning	entropy_src_rng	3.667m	18.137ms	1	1	100.00
V2	interrupts	entropy_src_rng	3.667m	18.137ms	1	1	100.00
		entropy_src_intr	37.000s	10.196ms	0	1	0.00
V2	alerts	entropy_src_rng	3.667m	18.137ms	1	1	100.00
		entropy_src_functional_alerts	11.000s	169.637us	1	1	100.00
V2	stress_all	entropy_src_stress_all	1.667m	15.333ms	1	1	100.00
V2	functional_errors	entropy_src_functional_errors	4.000s	100.341us	1	1	100.00
V2	firmware_ov_read_contiguous_data	entropy_src_fw_ov_contiguous	21.000s	343.282us	1	1	100.00
V2	intr_test	entropy_src_intr_test	4.000s	18.294us	1	1	100.00
V2	alert_test	entropy_src_alert_test	4.000s	17.369us	1	1	100.00
V2	tl_d_oob_addr_access	entropy_src_tl_errors	6.000s	482.537us	1	1	100.00
V2	tl_d_illegal_access	entropy_src_tl_errors	6.000s	482.537us	1	1	100.00
V2	tl_d_outstanding_access	entropy_src_csr_hw_reset	4.000s	63.196us	1	1	100.00
		entropy_src_csr_rw	3.000s	15.261us	1	1	100.00
		entropy_src_csr_aliasing	6.000s	263.649us	1	1	100.00
		entropy_src_same_csr_outstanding	4.000s	243.391us	1	1	100.00
V2	tl_d_partial_access	entropy_src_csr_hw_reset	4.000s	63.196us	1	1	100.00
		entropy_src_csr_rw	3.000s	15.261us	1	1	100.00
		entropy_src_csr_aliasing	6.000s	263.649us	1	1	100.00
		entropy_src_same_csr_outstanding	4.000s	243.391us	1	1	100.00
V2		TOTAL			11	12	91.67
V2S	tl_intg_err	entropy_src_sec_cm	4.000s	152.322us	1	1	100.00
		entropy_src_tl_intg_err	7.000s	125.790us	1	1	100.00
V2S	sec_cm_config_regwen	entropy_src_rng	3.667m	18.137ms	1	1	100.00
		entropy_src_cfg_regwen	4.000s	19.775us	1	1	100.00
V2S	sec_cm_config_mubi	entropy_src_rng	3.667m	18.137ms	1	1	100.00
V2S	sec_cm_config_redun	entropy_src_rng	3.667m	18.137ms	1	1	100.00
V2S	sec_cm_intersig_mubi	entropy_src_rng	3.667m	18.137ms	1	1	100.00
		entropy_src_fw_ov	4.283m	9.031ms	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	entropy_src_functional_errors	4.000s	100.341us	1	1	100.00
		entropy_src_sec_cm	4.000s	152.322us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	entropy_src_functional_errors	4.000s	100.341us	1	1	100.00
		entropy_src_sec_cm	4.000s	152.322us	1	1	100.00
V2S	sec_cm_rng_bkgn_chk	entropy_src_rng	3.667m	18.137ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	entropy_src_functional_errors	4.000s	100.341us	1	1	100.00
		entropy_src_sec_cm	4.000s	152.322us	1	1	100.00
V2S	sec_cm_ctr_redun	entropy_src_functional_errors	4.000s	100.341us	1	1	100.00
		entropy_src_sec_cm	4.000s	152.322us	1	1	100.00
V2S	sec_cm_ctr_local_esc	entropy_src_functional_errors	4.000s	100.341us	1	1	100.00
V2S	sec_cm_esfinal_rdata_bus_consistency	entropy_src_functional_alerts	11.000s	169.637us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	entropy_src_tl_intg_err	7.000s	125.790us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	external_health_tests	entropy_src_rng_with_xht_rsps	2.733m	8.037ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	22	95.45

Failure Buckets

• UVM_FATAL (entropy_src_intr_vseq.sv:290) [entropy_src_intr_vseq] timeout occurred! has 1 failures:
  • Test entropy_src_intr has 1 failures.

    • 0.entropy_src_intr.47503387000314100666770144060207302442893594300229719796990084331771537611822
      Line 152, in log /nightly/current_run/scratch/master/entropy_src-sim-xcelium/0.entropy_src_intr/latest/run.log

        UVM_FATAL @ 10196098921 ps: (entropy_src_intr_vseq.sv:290) [uvm_test_top.env.virtual_sequencer.entropy_src_intr_vseq] timeout occurred!
        UVM_INFO @ 10196098921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---