HMAC Simulation Results

Tuesday September 02 2025 21:26:11 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 6.150s 353.377us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.920s 118.727us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.730s 25.947us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.030s 724.707us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.940s 518.655us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.300s 38.501us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.730s 25.947us 1 1 100.00
hmac_csr_aliasing 5.940s 518.655us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 44.650s 18.257ms 1 1 100.00
V2 back_pressure hmac_back_pressure 44.490s 2.247ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.550s 700.076us 1 1 100.00
hmac_test_sha384_vectors 18.410s 238.275us 1 1 100.00
hmac_test_sha512_vectors 17.980s 398.559us 1 1 100.00
hmac_test_hmac256_vectors 6.950s 530.439us 1 1 100.00
hmac_test_hmac384_vectors 7.690s 1.039ms 1 1 100.00
hmac_test_hmac512_vectors 9.300s 1.153ms 1 1 100.00
V2 burst_wr hmac_burst_wr 17.440s 1.464ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 12.846m 21.293ms 1 1 100.00
V2 error hmac_error 1.473m 45.997ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.019m 29.610ms 1 1 100.00
V2 save_and_restore hmac_smoke 6.150s 353.377us 1 1 100.00
hmac_long_msg 44.650s 18.257ms 1 1 100.00
hmac_back_pressure 44.490s 2.247ms 1 1 100.00
hmac_datapath_stress 12.846m 21.293ms 1 1 100.00
hmac_burst_wr 17.440s 1.464ms 1 1 100.00
hmac_stress_all 18.509m 7.746ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 6.150s 353.377us 1 1 100.00
hmac_long_msg 44.650s 18.257ms 1 1 100.00
hmac_back_pressure 44.490s 2.247ms 1 1 100.00
hmac_datapath_stress 12.846m 21.293ms 1 1 100.00
hmac_wipe_secret 1.019m 29.610ms 1 1 100.00
hmac_test_sha256_vectors 7.550s 700.076us 1 1 100.00
hmac_test_sha384_vectors 18.410s 238.275us 1 1 100.00
hmac_test_sha512_vectors 17.980s 398.559us 1 1 100.00
hmac_test_hmac256_vectors 6.950s 530.439us 1 1 100.00
hmac_test_hmac384_vectors 7.690s 1.039ms 1 1 100.00
hmac_test_hmac512_vectors 9.300s 1.153ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 6.150s 353.377us 1 1 100.00
hmac_long_msg 44.650s 18.257ms 1 1 100.00
hmac_back_pressure 44.490s 2.247ms 1 1 100.00
hmac_datapath_stress 12.846m 21.293ms 1 1 100.00
hmac_burst_wr 17.440s 1.464ms 1 1 100.00
hmac_error 1.473m 45.997ms 1 1 100.00
hmac_wipe_secret 1.019m 29.610ms 1 1 100.00
hmac_test_sha256_vectors 7.550s 700.076us 1 1 100.00
hmac_test_sha384_vectors 18.410s 238.275us 1 1 100.00
hmac_test_sha512_vectors 17.980s 398.559us 1 1 100.00
hmac_test_hmac256_vectors 6.950s 530.439us 1 1 100.00
hmac_test_hmac384_vectors 7.690s 1.039ms 1 1 100.00
hmac_test_hmac512_vectors 9.300s 1.153ms 1 1 100.00
hmac_stress_all 18.509m 7.746ms 1 1 100.00
V2 stress_all hmac_stress_all 18.509m 7.746ms 1 1 100.00
V2 alert_test hmac_alert_test 0.590s 121.549us 1 1 100.00
V2 intr_test hmac_intr_test 0.650s 20.557us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.810s 172.265us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.810s 172.265us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.920s 118.727us 1 1 100.00
hmac_csr_rw 0.730s 25.947us 1 1 100.00
hmac_csr_aliasing 5.940s 518.655us 1 1 100.00
hmac_same_csr_outstanding 1.700s 108.988us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.920s 118.727us 1 1 100.00
hmac_csr_rw 0.730s 25.947us 1 1 100.00
hmac_csr_aliasing 5.940s 518.655us 1 1 100.00
hmac_same_csr_outstanding 1.700s 108.988us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.100s 125.784us 1 1 100.00
hmac_tl_intg_err 2.050s 335.765us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.050s 335.765us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 6.150s 353.377us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.410s 342.501us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.850m 3.858ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 0.860s 25.637us 1 1 100.00
TOTAL 28 28 100.00