I2C Simulation Results

Tuesday September 02 2025 21:26:11 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	31.790s	4.191ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	15.420s	780.485us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.820s	74.073us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.750s	27.390us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.250s	270.939us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.130s	31.434us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.950s	40.118us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.750s	27.390us	1	1	100.00
		i2c_csr_aliasing	1.130s	31.434us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.620s	76.329us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	9.475m	180.153ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	2.940s	977.649us	1	1	100.00
V2	host_override	i2c_host_override	0.650s	29.850us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.007m	12.634ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.747m	2.411ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.790s	143.139us	1	1	100.00
		i2c_host_fifo_fmt_empty	7.460s	2.158ms	1	1	100.00
		i2c_host_fifo_reset_rx	2.350s	688.695us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.449m	38.731ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	12.680s	1.786ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.230s	378.776us	0	1	0.00
V2	target_glitch	i2c_target_glitch	1.860s	404.953us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	3.966m	45.899ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.680s	995.495us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	4.760s	816.189us	1	1	100.00
		i2c_target_intr_smoke	2.920s	3.741ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.930s	353.935us	1	1	100.00
		i2c_target_fifo_reset_tx	0.710s	227.098us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	10.750s	39.458ms	1	1	100.00
		i2c_target_stress_rd	4.760s	816.189us	1	1	100.00
		i2c_target_intr_stress_wr	18.710s	17.327ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.430s	4.958ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	4.870s	3.346ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.680s	5.895ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.930s	1.392ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.960s	536.641us	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.960s	230.322us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.940s	977.649us	1	1	100.00
		i2c_host_perf_precise	1.780s	489.254us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	12.680s	1.786ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.760s	134.275us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.700s	457.736us	1	1	100.00
		i2c_target_nack_acqfull_addr	1.830s	520.841us	1	1	100.00
		i2c_target_nack_txstretch	1.090s	151.915us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	7.640s	586.001us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.530s	1.576ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.590s	31.095us	1	1	100.00
V2	intr_test	i2c_intr_test	0.740s	22.008us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.210s	163.537us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.210s	163.537us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.820s	74.073us	1	1	100.00
		i2c_csr_rw	0.750s	27.390us	1	1	100.00
		i2c_csr_aliasing	1.130s	31.434us	1	1	100.00
		i2c_same_csr_outstanding	1.030s	62.903us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.820s	74.073us	1	1	100.00
		i2c_csr_rw	0.750s	27.390us	1	1	100.00
		i2c_csr_aliasing	1.130s	31.434us	1	1	100.00
		i2c_same_csr_outstanding	1.030s	62.903us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	1.190s	257.880us	1	1	100.00
		i2c_sec_cm	0.850s	134.667us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.190s	257.880us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	14.120s	970.297us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.250s	1.350ms	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	8.680s	770.725us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.93518363498331635387069318688640406895966527895208887834913928228756655859824
      Line 97, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 970297468 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 970297468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.24526468843891552687453539687413669931259625951048690763947878035678538721273
      Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 770724574 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 770724574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.20811212179433818354842948984799443408488995189577297991808584081066400410207
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  76329334 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  76329334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.65065647932919334632331564929524342169501571309588439967337804941811482064542
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 404952760 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 404952760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.8133021862599846756076267555395285415504221356579482795977300254728095117513
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 1350147808 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 56 [0x38])
        UVM_INFO @ 1350147808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.71643477489884242050204572040394484198350375418171826720869672699583446916397
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 378775656 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @72089