KEYMGR Simulation Results

Tuesday September 02 2025 21:26:11 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 2.320s 400.537us 1 1 100.00
V1 random keymgr_random 3.070s 413.218us 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.090s 66.548us 1 1 100.00
V1 csr_rw keymgr_csr_rw 1.220s 29.854us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 22.290s 1.500ms 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 3.880s 245.497us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.540s 29.296us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.220s 29.854us 1 1 100.00
keymgr_csr_aliasing 3.880s 245.497us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 9.250s 249.131us 1 1 100.00
V2 sideload keymgr_sideload 1.670s 54.722us 1 1 100.00
keymgr_sideload_kmac 4.480s 956.507us 1 1 100.00
keymgr_sideload_aes 2.530s 299.150us 1 1 100.00
keymgr_sideload_otbn 1.620s 48.217us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 1.710s 159.319us 1 1 100.00
V2 lc_disable keymgr_lc_disable 2.360s 329.222us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 3.090s 181.691us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 3.120s 174.713us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 3.990s 274.096us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 1.960s 78.162us 1 1 100.00
V2 stress_all keymgr_stress_all 8.290s 452.874us 1 1 100.00
V2 intr_test keymgr_intr_test 0.710s 23.863us 1 1 100.00
V2 alert_test keymgr_alert_test 0.930s 13.295us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 2.550s 196.605us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 2.550s 196.605us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.090s 66.548us 1 1 100.00
keymgr_csr_rw 1.220s 29.854us 1 1 100.00
keymgr_csr_aliasing 3.880s 245.497us 1 1 100.00
keymgr_same_csr_outstanding 1.540s 93.872us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.090s 66.548us 1 1 100.00
keymgr_csr_rw 1.220s 29.854us 1 1 100.00
keymgr_csr_aliasing 3.880s 245.497us 1 1 100.00
keymgr_same_csr_outstanding 1.540s 93.872us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 4.330s 394.565us 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 4.330s 394.565us 1 1 100.00
keymgr_tl_intg_err 3.040s 597.688us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 1.990s 250.245us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 1.990s 250.245us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 1.990s 250.245us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 1.990s 250.245us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 4.330s 5.277ms 1 1 100.00
V2S prim_count_check keymgr_sec_cm 4.330s 394.565us 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 4.330s 394.565us 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 3.040s 597.688us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 1.990s 250.245us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 9.250s 249.131us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 3.070s 413.218us 1 1 100.00
keymgr_csr_rw 1.220s 29.854us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 3.070s 413.218us 1 1 100.00
keymgr_csr_rw 1.220s 29.854us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 3.070s 413.218us 1 1 100.00
keymgr_csr_rw 1.220s 29.854us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 2.360s 329.222us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 3.990s 274.096us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 3.990s 274.096us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 3.070s 413.218us 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 2.000s 1.345ms 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 4.330s 394.565us 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 4.330s 394.565us 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 4.330s 394.565us 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 2.880s 522.606us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 2.360s 329.222us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 4.330s 394.565us 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 4.330s 394.565us 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 4.330s 394.565us 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 2.880s 522.606us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 2.880s 522.606us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 4.330s 394.565us 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 2.880s 522.606us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 4.330s 394.565us 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 2.880s 522.606us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 11.960s 878.609us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00