KMAC/UNMASKED Simulation Results

Tuesday September 02 2025 21:26:11 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	28.340s	1.977ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.800s	232.261us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.790s	28.620us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.640s	3.352ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.090s	1.079ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.180s	69.747us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.790s	28.620us	1	1	100.00
		kmac_csr_aliasing	3.090s	1.079ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.910s	42.181us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.240s	121.835us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	5.644m	14.654ms	1	1	100.00
V2	burst_write	kmac_burst_write	10.610s	1.660ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	20.207m	17.898ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.870s	4.713ms	1	1	100.00
		kmac_test_vectors_sha3_384	14.790s	1.889ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.160s	273.360us	1	1	100.00
		kmac_test_vectors_shake_128	33.688m	225.051ms	1	1	100.00
		kmac_test_vectors_shake_256	1.185m	19.239ms	1	1	100.00
		kmac_test_vectors_kmac	1.400s	265.840us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.550s	32.010us	1	1	100.00
V2	sideload	kmac_sideload	2.833m	16.557ms	1	1	100.00
V2	app	kmac_app	5.870s	2.843ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	46.070s	3.956ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.680m	15.695ms	1	1	100.00
V2	error	kmac_error	3.424m	21.720ms	1	1	100.00
V2	key_error	kmac_key_error	4.120s	1.971ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.149m	10.111ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	18.620s	2.644ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.600s	108.420us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	4.930s	589.782us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	11.540s	1.413ms	1	1	100.00
V2	stress_all	kmac_stress_all	8.402m	18.003ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.700s	29.826us	1	1	100.00
V2	alert_test	kmac_alert_test	0.880s	79.679us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.760s	217.091us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.760s	217.091us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.800s	232.261us	1	1	100.00
		kmac_csr_rw	0.790s	28.620us	1	1	100.00
		kmac_csr_aliasing	3.090s	1.079ms	1	1	100.00
		kmac_same_csr_outstanding	1.820s	39.775us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.800s	232.261us	1	1	100.00
		kmac_csr_rw	0.790s	28.620us	1	1	100.00
		kmac_csr_aliasing	3.090s	1.079ms	1	1	100.00
		kmac_same_csr_outstanding	1.820s	39.775us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.310s	78.073us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.310s	78.073us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.310s	78.073us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.310s	78.073us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.060s	235.028us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	56.660s	23.072ms	1	1	100.00
		kmac_tl_intg_err	1.750s	216.645us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.750s	216.645us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	11.540s	1.413ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	28.340s	1.977ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.833m	16.557ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.310s	78.073us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	56.660s	23.072ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	56.660s	23.072ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	56.660s	23.072ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	28.340s	1.977ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	11.540s	1.413ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	56.660s	23.072ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.232m	15.454ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	28.340s	1.977ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.550m	5.524ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.5561377618188238806035565533203985101131350308992117317041544009391328146844
      Line 89, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10111136042 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x80235000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
        UVM_INFO @ 10111136042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:945) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.7004921495729945399338604073674839062400367039701962511495539327361095959535
      Line 339, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5524140775 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5524140775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---