OTBN Simulation Results

Tuesday September 02 2025 21:26:11 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	46.517us	1	1	100.00
V1	single_binary	otbn_single	11.000s	22.722us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	4.000s	198.002us	1	1	100.00
V1	csr_rw	otbn_csr_rw	5.000s	48.258us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	130.479us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	31.538us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	67.142us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	48.258us	1	1	100.00
		otbn_csr_aliasing	5.000s	31.538us	1	1	100.00
V1	mem_walk	otbn_mem_walk	31.000s	431.106us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	19.000s	731.902us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	19.000s	277.310us	1	1	100.00
V2	multi_error	otbn_multi_err	45.000s	172.150us	1	1	100.00
V2	back_to_back	otbn_multi	33.000s	174.969us	1	1	100.00
V2	stress_all	otbn_stress_all	43.000s	671.779us	1	1	100.00
V2	lc_escalation	otbn_escalate	7.000s	46.807us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	21.457us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	6.000s	39.494us	1	1	100.00
V2	alert_test	otbn_alert_test	5.000s	60.204us	1	1	100.00
V2	intr_test	otbn_intr_test	4.000s	23.634us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	33.654us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	33.654us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	4.000s	198.002us	1	1	100.00
		otbn_csr_rw	5.000s	48.258us	1	1	100.00
		otbn_csr_aliasing	5.000s	31.538us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	24.379us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	4.000s	198.002us	1	1	100.00
		otbn_csr_rw	5.000s	48.258us	1	1	100.00
		otbn_csr_aliasing	5.000s	31.538us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	24.379us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	8.000s	25.430us	1	1	100.00
		otbn_dmem_err	7.000s	95.738us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	8.000s	111.283us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	284.726us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	57.157us	1	1	100.00
		otbn_urnd_err	6.000s	10.032us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	5.000s	56.815us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	6.000s	21.857us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	6.000s	16.521us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	8.000s	24.695us	0	1	0.00
		otbn_tl_intg_err	16.000s	106.913us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	20.000s	524.532us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.000s	24.695us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	8.000s	24.695us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	46.517us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	7.000s	95.738us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	8.000s	25.430us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	16.000s	106.913us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	7.000s	46.807us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	8.000s	25.430us	1	1	100.00
		otbn_dmem_err	7.000s	95.738us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	21.457us	1	1	100.00
		otbn_illegal_mem_acc	5.000s	56.815us	1	1	100.00
		otbn_sec_cm	8.000s	24.695us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.000s	24.695us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	11.000s	22.722us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	8.000s	25.430us	1	1	100.00
		otbn_dmem_err	7.000s	95.738us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	21.457us	1	1	100.00
		otbn_illegal_mem_acc	5.000s	56.815us	1	1	100.00
		otbn_sec_cm	8.000s	24.695us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.000s	24.695us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	7.000s	46.807us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	8.000s	25.430us	1	1	100.00
		otbn_dmem_err	7.000s	95.738us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	21.457us	1	1	100.00
		otbn_illegal_mem_acc	5.000s	56.815us	1	1	100.00
		otbn_sec_cm	8.000s	24.695us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.000s	24.695us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	11.000s	22.722us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	7.000s	14.050us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	20.934us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	15.000s	225.828us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	15.000s	225.828us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	9.000s	51.603us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.000s	24.695us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.000s	24.695us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	8.000s	250.367us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.000s	24.695us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.000s	24.695us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	6.000s	21.834us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	6.000s	21.834us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	6.000s	12.739us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	11.000s	22.722us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	11.000s	22.722us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	11.000s	22.722us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	33.000s	174.969us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	11.000s	22.722us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	11.000s	22.722us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	128.662us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	11.000s	22.722us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.000s	24.695us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	8.000s	97.046us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	41	92.68

Failure Buckets

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.8128576957511804225103683406540072244510226742708136409099608189116871934946
      Line 145, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  97046247 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @  97046247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.87304436730957981962184118243485411637686306333020791845005390639124020025375
      Line 110, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12738635 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  12738635 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  12738635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.10106944858187152832121505427597481309326935248981914254190482569075326763515
      Line 104, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 24695490 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 24695490 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 24695490 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 24695490 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 24695490 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed