| V1 |
random |
rv_timer_random |
0.600s |
16.402us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
0.660s |
60.158us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
0.680s |
15.251us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
2.060s |
289.429us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
0.850s |
25.015us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
0.710s |
19.818us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
0.680s |
15.251us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.850s |
25.015us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
5.350s |
12.075ms |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
0.900s |
3.490ms |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
2.700s |
6.346ms |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
2.700s |
6.346ms |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
2.070s |
5.537ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
0.510s |
63.426us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
0.620s |
24.012us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
1.810s |
133.760us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
1.810s |
133.760us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
0.660s |
60.158us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
0.680s |
15.251us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.850s |
25.015us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
0.690s |
32.542us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
0.660s |
60.158us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
0.680s |
15.251us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
0.850s |
25.015us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
0.690s |
32.542us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
0.660s |
133.345us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
1.070s |
160.164us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
1.070s |
160.164us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
0.480s |
42.867us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
0.590s |
16.189us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
40.740s |
14.563ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |