| V1 |
smoke |
spi_host_smoke |
26.000s |
2.726ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
spi_host_csr_hw_reset |
2.000s |
51.287us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
spi_host_csr_rw |
3.000s |
104.794us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
spi_host_csr_bit_bash |
3.000s |
109.253us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
spi_host_csr_aliasing |
4.000s |
30.841us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
spi_host_csr_mem_rw_with_rand_reset |
3.000s |
49.539us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
spi_host_csr_rw |
3.000s |
104.794us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
4.000s |
30.841us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
spi_host_mem_walk |
3.000s |
46.566us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
spi_host_mem_partial_access |
3.000s |
41.549us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
performance |
spi_host_performance |
3.000s |
23.526us |
1 |
1 |
100.00 |
| V2 |
error_event_intr |
spi_host_overflow_underflow |
4.000s |
26.310us |
1 |
1 |
100.00 |
|
|
spi_host_error_cmd |
3.000s |
19.568us |
1 |
1 |
100.00 |
|
|
spi_host_event |
10.000s |
2.684ms |
1 |
1 |
100.00 |
| V2 |
clock_rate |
spi_host_speed |
6.000s |
99.174us |
1 |
1 |
100.00 |
| V2 |
speed |
spi_host_speed |
6.000s |
99.174us |
1 |
1 |
100.00 |
| V2 |
chip_select_timing |
spi_host_speed |
6.000s |
99.174us |
1 |
1 |
100.00 |
| V2 |
sw_reset |
spi_host_sw_reset |
5.000s |
108.049us |
1 |
1 |
100.00 |
| V2 |
passthrough_mode |
spi_host_passthrough_mode |
3.000s |
121.234us |
1 |
1 |
100.00 |
| V2 |
cpol_cpha |
spi_host_speed |
6.000s |
99.174us |
1 |
1 |
100.00 |
| V2 |
full_cycle |
spi_host_speed |
6.000s |
99.174us |
1 |
1 |
100.00 |
| V2 |
duplex |
spi_host_smoke |
26.000s |
2.726ms |
1 |
1 |
100.00 |
| V2 |
tx_rx_only |
spi_host_smoke |
26.000s |
2.726ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
spi_host_stress_all |
3.000s |
62.477us |
1 |
1 |
100.00 |
| V2 |
spien |
spi_host_spien |
5.000s |
291.907us |
1 |
1 |
100.00 |
| V2 |
stall |
spi_host_status_stall |
25.000s |
3.842ms |
1 |
1 |
100.00 |
| V2 |
Idlecsbactive |
spi_host_idlecsbactive |
3.000s |
112.710us |
1 |
1 |
100.00 |
| V2 |
data_fifo_status |
spi_host_overflow_underflow |
4.000s |
26.310us |
1 |
1 |
100.00 |
| V2 |
alert_test |
spi_host_alert_test |
3.000s |
42.718us |
1 |
1 |
100.00 |
| V2 |
intr_test |
spi_host_intr_test |
3.000s |
50.962us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
spi_host_tl_errors |
4.000s |
93.958us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
spi_host_tl_errors |
4.000s |
93.958us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
spi_host_csr_hw_reset |
2.000s |
51.287us |
1 |
1 |
100.00 |
|
|
spi_host_csr_rw |
3.000s |
104.794us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
4.000s |
30.841us |
1 |
1 |
100.00 |
|
|
spi_host_same_csr_outstanding |
3.000s |
114.565us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
spi_host_csr_hw_reset |
2.000s |
51.287us |
1 |
1 |
100.00 |
|
|
spi_host_csr_rw |
3.000s |
104.794us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
4.000s |
30.841us |
1 |
1 |
100.00 |
|
|
spi_host_same_csr_outstanding |
3.000s |
114.565us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
15 |
15 |
100.00 |
| V2S |
tl_intg_err |
spi_host_tl_intg_err |
4.000s |
129.251us |
1 |
1 |
100.00 |
|
|
spi_host_sec_cm |
3.000s |
247.267us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
spi_host_tl_intg_err |
4.000s |
129.251us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
spi_host_upper_range_clkdiv |
50.000s |
3.020ms |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
26 |
26 |
100.00 |