UART Simulation Results

Tuesday September 02 2025 21:26:11 UTC

GitHub Revision: a14e715

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.040s	547.595us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.730s	42.562us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.650s	15.986us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.220s	135.240us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.650s	15.955us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.840s	22.444us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	15.986us	1	1	100.00
		uart_csr_aliasing	0.650s	15.955us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	45.840s	45.172ms	1	1	100.00
V2	parity	uart_smoke	1.040s	547.595us	1	1	100.00
		uart_tx_rx	45.840s	45.172ms	1	1	100.00
V2	parity_error	uart_intr	57.440s	445.847ms	1	1	100.00
		uart_rx_parity_err	10.830s	25.527ms	1	1	100.00
V2	watermark	uart_tx_rx	45.840s	45.172ms	1	1	100.00
		uart_intr	57.440s	445.847ms	1	1	100.00
V2	fifo_full	uart_fifo_full	11.900s	53.335ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	23.480s	65.358ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	23.610s	182.989ms	1	1	100.00
V2	rx_frame_err	uart_intr	57.440s	445.847ms	1	1	100.00
V2	rx_break_err	uart_intr	57.440s	445.847ms	1	1	100.00
V2	rx_timeout	uart_intr	57.440s	445.847ms	1	1	100.00
V2	perf	uart_perf	11.538m	21.132ms	1	1	100.00
V2	sys_loopback	uart_loopback	1.830s	3.025ms	1	1	100.00
V2	line_loopback	uart_loopback	1.830s	3.025ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	2.360s	5.322ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.000s	3.541ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.420s	1.231ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	1.930s	2.106ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	9.279m	138.410ms	1	1	100.00
V2	stress_all	uart_stress_all	2.416m	196.780ms	1	1	100.00
V2	alert_test	uart_alert_test	0.650s	13.109us	1	1	100.00
V2	intr_test	uart_intr_test	0.590s	21.979us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.530s	86.569us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.530s	86.569us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.730s	42.562us	1	1	100.00
		uart_csr_rw	0.650s	15.986us	1	1	100.00
		uart_csr_aliasing	0.650s	15.955us	1	1	100.00
		uart_same_csr_outstanding	0.770s	50.967us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.730s	42.562us	1	1	100.00
		uart_csr_rw	0.650s	15.986us	1	1	100.00
		uart_csr_aliasing	0.650s	15.955us	1	1	100.00
		uart_same_csr_outstanding	0.770s	50.967us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.740s	40.645us	1	1	100.00
		uart_tl_intg_err	1.200s	168.104us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.200s	168.104us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	18.960s	10.850ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.79994411684320147251737250394993003686306513920188236736079110469044153038916
      Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 3749785065 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 3749830520 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 3749875975 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (251 [0xfb] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 4206471450 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 13,                                 clk_pulses: 0
        UVM_ERROR @ 4206516905 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty