CHIP Simulation Results

Tuesday September 02 2025 21:26:11 UTC

GitHub Revision: `a14e715`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.991m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.991m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.339m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.233m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	58.398s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.408m	5.409ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.408m	5.409ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.408m	5.409ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	29.910s	10.240us	0	1	0.00
		chip_sw_example_manufacturer	2.251m		0	1	0.00
		chip_sw_example_concurrency	4.180m	4.690ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.703s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.520s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.230s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.230s		0	1	0.00
V1	xbar_smoke	xbar_smoke	10.250s	10.914us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.848m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.853m	7.420ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	6.125m	5.687ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	24.453s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	22.800s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	47.000s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	26.469s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	2.950s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.950s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.074m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.444m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.292m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.292m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.951m	3.718ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.843m	3.207ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.580m	13.958ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.971s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	13.333s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.324m	9.607ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	7.176m	5.864ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	25.979m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	25.979m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.845s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.093m	3.887ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.093m	3.887ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.396m	18.027ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.056m	4.056ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.466m	5.393ms	1	1	100.00
		chip_sw_aes_idle	4.659m	4.701ms	1	1	100.00
		chip_sw_hmac_enc_idle	6.136m	5.936ms	1	1	100.00
		chip_sw_kmac_idle	5.281m	5.479ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.273m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	13.639m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	15.198m	11.425ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	12.376m	12.027ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	14.726s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.427s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.909s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.769s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.667s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.639s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.557s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.726s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.427s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.909s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.769s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.667s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.639s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.557s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.665s		0	1	0.00
		chip_sw_aes_enc_jitter_en	44.790s	10.240us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	48.820s	10.400us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.240s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	44.730s	10.120us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.556s		0	1	0.00
		chip_sw_clkmgr_jitter	4.049m	4.110ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.656m	5.509ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.010s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	39.010s	10.380us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	37.770s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	37.580s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	36.380s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	36.520s	10.360us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	13.554s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.305s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.394s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	13.573s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	22.704m	13.960ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.506m	15.120ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.093m	3.887ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.855s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.506m	15.120ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	22.369s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	19.093s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	17.518s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	17.020s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	16.489s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	22.704m	13.960ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.580m	13.958ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	24.637m	20.027ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.151m	9.154ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	9.083m	5.953ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.162m	5.395ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	22.704m	13.960ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	14.315s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	13.551s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	22.704m	13.960ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.130s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	9.083m	5.953ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.380s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.509s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.585s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	15.598s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.617s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	14.086s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	13.551s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	14.096s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	24.519s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	14.096s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	14.096s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	14.096s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	9.763m	9.373ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.116s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	20.845s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	36.502s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	34.884s		0	1	0.00
		chip_sw_lc_ctrl_transition	14.096s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.144m	6.953ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.579m	10.886ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	16.570s		0	1	0.00
		chip_prim_tl_access	13.366m	21.498ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.726s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.427s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.909s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.769s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.667s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.639s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.557s		0	1	0.00
		chip_rv_dm_lc_disabled	6.324m	9.607ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.013m	3.211ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	44.790s	10.240us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.027m	4.138ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.659m	4.701ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.672m	4.267ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	48.820s	10.400us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.136m	5.936ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.673m	3.585ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.554m	3.763ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	44.730s	10.120us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.144m	6.953ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	14.096s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	36.880s	10.340us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.611m	4.152ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.281m	5.479ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.489s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.489s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.029s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.269m	5.551ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.680s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.144m	6.953ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.240s	10.240us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	15.477s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.665s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.466m	5.393ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.466m	5.393ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.466m	5.393ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.856m	6.496ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.579m	10.886ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.579m	10.886ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.690m	7.164ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.556s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	16.570s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	22.704m	13.960ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.292m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	14.096s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.856m	6.496ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.144m	6.953ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.690m	7.164ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.710m	5.006ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.856m	6.496ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.144m	6.953ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.690m	7.164ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.710m	5.006ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	14.096s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	13.277s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	24.519s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.116s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	20.845s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	36.502s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	34.884s		0	1	0.00
		chip_sw_lc_ctrl_transition	14.096s		0	1	0.00
		chip_prim_tl_access	13.366m	21.498ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	13.366m	21.498ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	15.291s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	23.588s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.305s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.665s		0	1	0.00
		chip_sw_aes_enc_jitter_en	44.790s	10.240us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	48.820s	10.400us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.240s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	44.730s	10.120us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.556s		0	1	0.00
		chip_sw_clkmgr_jitter	4.049m	4.110ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	9.163m	7.915ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	9.163m	7.915ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.613m	4.883ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.828m	4.121ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.971m	5.456ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.791m	4.697ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.969m	3.681ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.858m	5.579ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.710m	5.006ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	24.637m	20.027ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	24.637m	20.027ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.538m	4.583ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.345m	5.313ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.889m	5.479ms	1	1	100.00
		chip_sw_csrng_smoketest	3.412m	3.071ms	1	1	100.00
		chip_sw_gpio_smoketest	3.702m	3.491ms	1	1	100.00
		chip_sw_hmac_smoketest	4.936m	5.599ms	1	1	100.00
		chip_sw_kmac_smoketest	3.866m	3.476ms	1	1	100.00
		chip_sw_otbn_smoketest	4.681m	4.088ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	4.273m	4.848ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.380m	4.471ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.630m	7.015ms	1	1	100.00
		chip_sw_rstmgr_smoketest	4.003m	5.118ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.167m	5.202ms	1	1	100.00
		chip_sw_uart_smoketest	3.534m	5.197ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.391s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.703s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.848m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.861s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.157m	5.275ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.210m	5.227ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.944m	5.816ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.688m	6.052ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.230s		0	1	0.00
		chip_rv_dm_lc_disabled	6.324m	9.607ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.802s		0	1	0.00
		chip_sw_lc_walkthrough_prod	15.005s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.018s		0	1	0.00
		chip_sw_lc_walkthrough_rma	12.143s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.230s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	15.025s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	17.942s		0	1	0.00
		rom_volatile_raw_unlock	11.375s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.675s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.723m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.107m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.653m	4.225ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.653m	4.225ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.230s		0	1	0.00
		chip_same_csr_outstanding	13.640s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.230s		0	1	0.00
		chip_same_csr_outstanding	13.640s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	28.620s	25.875us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.320s	12.057us	1	1	100.00
		xbar_smoke_large_delays	5.193m	2.689ms	1	1	100.00
		xbar_smoke_slow_rsp	5.373m	1.961ms	1	1	100.00
		xbar_random_zero_delays	29.830s	25.482us	1	1	100.00
		xbar_random_large_delays	14.717m	7.264ms	1	1	100.00
		xbar_random_slow_rsp	15.279m	5.267ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	33.780s	22.871us	1	1	100.00
		xbar_error_and_unmapped_addr	14.220s	13.474us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	24.870s	30.526us	1	1	100.00
		xbar_error_and_unmapped_addr	14.220s	13.474us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.466m	719.798us	1	1	100.00
		xbar_access_same_device_slow_rsp	53.706m	21.354ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	10.520s	12.105us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	5.191m	235.329us	1	1	100.00
		xbar_stress_all_with_error	10.774m	551.443us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	22.345m	618.965us	1	1	100.00
		xbar_stress_all_with_reset_error	1.491m	111.966us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.701s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.892s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.216s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.350s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.165s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.758s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.199s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.210s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.507s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.999s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.101s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.106s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.258s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.317s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.755s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.627s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.651s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.701s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.396s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.287s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.932s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.779s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.659s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.506s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.271s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.254s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.227s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.493s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.691s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.576s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.967s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.133s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.696s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.855s		0	1	0.00
		rom_e2e_asm_init_dev	11.394s		0	1	0.00
		rom_e2e_asm_init_prod	11.885s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.456s		0	1	0.00
		rom_e2e_asm_init_rma	12.457s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.959s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.954s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.759s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.805s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.471m	4.015ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.200m	3.893ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.417s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.894s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.536s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.491s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	22.704m	13.960ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	16.177s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.512m	14.734ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	13.064s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.796s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.417s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.894s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.536s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.090s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.645s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.755s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.624s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.942m	13.546ms	1	1	100.00
		chip_sw_entropy_src_kat_test	4.382m	4.982ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	4.817m	5.170ms	1	1	100.00
		chip_plic_all_irqs_0	10.549m	7.538ms	1	1	100.00
		chip_plic_all_irqs_10	10.716m	7.690ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.329m	4.449ms	1	1	100.00
		chip_sw_dma_abort	4.458m	5.426ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.916s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.191s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.324s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.812s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.543s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.627s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.429s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.706s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.018s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.654s		0	1	0.00
		chip_sw_entropy_src_smoketest	5.057m	4.909ms	1	1	100.00
		chip_sw_mbx_smoketest	4.966m	5.579ms	1	1	100.00
		TOTAL			80	250	32.00

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.15162687058412617315164531595200418832500202435350300916793923951636140949886
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 124.273s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.28368677301494556698272046571543054401283144765952128062125637964309459169466
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 126.733s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.61619988968563531430072426113068070316362165067956246327747016707576361916613
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 112.150s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.108283120016813639059659166985642691452174128829503755553277944447681133943140
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 134.203s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.66718259564161594366523970646785042283455784721386728020055275471506692364662
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 108.644s, Critical Path: 0.00s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.67794751222047596999735078459577502525542259321836393751764857359663988609946
    Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.56852907221961413075263637332598469100347554340551782539825340101260291317825
    Line 375, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.72063947903029923256039714957691671930194439190596340909529769067069749222536
    Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.49679796259950181874084547146273708226968776151140905178987786105005890798242
    Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.69435509613242567286990527661199464954463868817602526959680148383743733086310
    Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.47774499544765617075235969515175853317983107971510302156817121473160507532398
Line 422, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20026.928902 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20026.928902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.22537829912457476108677642952598267758727872845344154266509885983680853942387
Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.600804 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.600804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.44463561205415938911749803092589252067853137559483070310809987829469066189348
Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18026.842340 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.842340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.58346626431554618367397854873981696337499537171172701467181136937810077212385
Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12026.785405 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.785405 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.83562197230478018539539544741975806039102606974190462562163061519399577630593
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.13467216534422270873152224747276338494262234840899230828159331970495608111915
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.16530359606477919173666346622131658688631580719965413172931369905305521118518
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.71395218573126912480493115544879789191285440613560115616540357328989573673584
Line 429, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6953.292325 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (7622631525579977910768086262313238833989345940261059941963068470105020907592 [0x10da41ad641bea799264db3fd200c93c5478c4c3ddfc70427001181e41cd4048] vs 27362337728749375025679726067579952991584919645701261861903007344971179800188 [0x3c7e88ca01b2f14fac148f46a093e848de489e42eba769b964a2c98d3ceab67c])
  UVM_INFO @ 6953.292325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.47422689575864245707986013955514950496436688406002989775057965816648408827733
Line 429, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 9372.981368 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (1140392883388219176721526177090005486771085917132244654326670259862901650700 [0x2857082f8fec4bbb96812fc7af0053869d9ccdad16e2c75e9c9b28f858c750c] vs 113756119502449886698178980848757371424022382749767323791665436100748894744564 [0xfb7fae955e42a647949762509870de9b7c86e9aac6372623839e0f593e4b2ff4])
  UVM_INFO @ 9372.981368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:
- Test chip_sw_clkmgr_off_aes_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_aes_trans.46038149765294915264218831779463396884505520102773846807523876879452294655116
    Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
```
  UVM_ERROR @ 12018.580440 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.580440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_hmac_trans.21294543634668005024820817437971795607836015735415689011316985170174606702111
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
```
  UVM_ERROR @ 12018.380862 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.380862 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47274) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.72934063369432326013098604865391841809261369168174468635047201894867382207941
Line 6260, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3718.059168 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47274) { a_addr: 'h30480000  a_data: 'h5951f1f7  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h1  a_user: 'h2489d  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3718.059168 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.24035096225515714863172774005828687547231582296688544695761066077588716737876
Line 6260, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3207.179307 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47274) { a_addr: 'h30480000  a_data: 'hced2c435  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h20  a_opcode: 'h1  a_user: 'h248e2  d_param: 'h0  d_source: 'h20  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3207.179307 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.21799047017863779545426173653868203350327951014570478173888385909303033404532
    Line 569, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.22883440381830959753001805634931725367436640600557219246044981825928659023807
    Line 451, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5686.845960 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5686.845960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.35857623343546276076381937424731982079855561117842341782403189556626442269998
    Line 646, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 5953.303720 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 5953.303720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.55187871109875202309915068450440969040085315889286470836853413717835803465528
    Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4882.577425 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4882.577425 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.86806857250001139936237905491848322412626350464127243966768209970704054431520
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4120.901274 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4120.901274 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.105339009692389966515302879278810886916924783767638039995189389668030894769072
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 3886.556112 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 3886.556112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.10204653252930081735357131485145690824751646691684164843794972228684207239121
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4697.029230 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4697.029230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.87007281297840155384146163240845640283987575198605712363892795528367452192399
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.2580547005238357833092842645977461371067248886623598201148304056827108737179
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4224.696272 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4224.696272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.112032594156278465299935604366760787941593157282303162944614535432949231963445
    Line 374, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13958.443912 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13958.443912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.83158761296948273694884049297024297675046978059049864575505895969498817272301
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.103620880987953116216326050402830197889066443851749419795646843019800442752193
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5426.479656 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5426.479656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```