DMA Simulation Results

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: 72c264a

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	6.000s	289.772us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	6.000s	675.771us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	6.000s	282.544us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	3.000s	188.130us	1	1	100.00
V1	csr_rw	dma_csr_rw	3.000s	16.277us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	7.000s	2.491ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	4.000s	77.794us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	3.000s	19.728us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	3.000s	16.277us	1	1	100.00
		dma_csr_aliasing	4.000s	77.794us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.567m	10.285ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	5.517m	115.291ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	5.517m	130.900ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	5.517m	130.900ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	5.517m	115.291ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	17.417m	397.627ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	5.517m	130.900ms	1	1	100.00
V2	dma_abort	dma_abort	12.000s	1.829ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.233m	21.323ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	25.201us	1	1	100.00
V2	intr_test	dma_intr_test	2.000s	31.160us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	386.693us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	386.693us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	3.000s	188.130us	1	1	100.00
		dma_csr_rw	3.000s	16.277us	1	1	100.00
		dma_csr_aliasing	4.000s	77.794us	1	1	100.00
		dma_same_csr_outstanding	4.000s	527.899us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	3.000s	188.130us	1	1	100.00
		dma_csr_rw	3.000s	16.277us	1	1	100.00
		dma_csr_aliasing	4.000s	77.794us	1	1	100.00
		dma_same_csr_outstanding	4.000s	527.899us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	19.000s	705.728us	1	1	100.00
		dma_generic_stress	17.417m	397.627ms	1	1	100.00
		dma_handshake_stress	5.517m	130.900ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	7.000s	582.030us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	222.682us	1	1	100.00
		dma_sec_cm	2.000s	149.067us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.183m	14.943ms	1	1	100.00
		dma_longer_transfer	5.000s	511.949us	1	1	100.00
		dma_stress_all_with_rand_reset	17.000s	1.636ms	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:946) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.15203545870736438328820616566241194157708167224920166460971433840141746847287
      Line 122, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1635923703ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1635923703ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---