EDN Simulation Results

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: 72c264a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.910s 20.814us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.800s 29.693us 1 1 100.00
V1 csr_rw edn_csr_rw 0.720s 14.681us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.040s 366.206us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.120s 64.728us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.020s 22.940us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.720s 14.681us 1 1 100.00
edn_csr_aliasing 1.120s 64.728us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.040s 57.911us 1 1 100.00
V2 csrng_commands edn_genbits 1.040s 57.911us 1 1 100.00
V2 genbits edn_genbits 1.040s 57.911us 1 1 100.00
V2 interrupts edn_intr 0.830s 36.365us 1 1 100.00
V2 alerts edn_alert 0.950s 44.457us 1 1 100.00
V2 errs edn_err 0.790s 35.286us 1 1 100.00
V2 disable edn_disable 0.750s 14.137us 1 1 100.00
edn_disable_auto_req_mode 1.070s 49.268us 1 1 100.00
V2 stress_all edn_stress_all 2.420s 306.305us 1 1 100.00
V2 intr_test edn_intr_test 0.700s 30.477us 1 1 100.00
V2 alert_test edn_alert_test 0.860s 92.901us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 1.740s 438.139us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 1.740s 438.139us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.800s 29.693us 1 1 100.00
edn_csr_rw 0.720s 14.681us 1 1 100.00
edn_csr_aliasing 1.120s 64.728us 1 1 100.00
edn_same_csr_outstanding 0.930s 21.710us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.800s 29.693us 1 1 100.00
edn_csr_rw 0.720s 14.681us 1 1 100.00
edn_csr_aliasing 1.120s 64.728us 1 1 100.00
edn_same_csr_outstanding 0.930s 21.710us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.220s 1.867ms 1 1 100.00
edn_tl_intg_err 1.430s 62.396us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.810s 54.573us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 0.950s 44.457us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.220s 1.867ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.220s 1.867ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.220s 1.867ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.220s 1.867ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 0.950s 44.457us 1 1 100.00
edn_sec_cm 6.220s 1.867ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 0.950s 44.457us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.430s 62.396us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets