ENTROPY_SRC/RNG_16BITS Simulation Results

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: 72c264a

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 3.000s 29.938us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 91.566us 1 1 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 306.707us 1 1 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 12.000s 1.993ms 1 1 100.00
V1 csr_aliasing entropy_src_csr_aliasing 5.000s 114.697us 1 1 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 217.901us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 306.707us 1 1 100.00
entropy_src_csr_aliasing 5.000s 114.697us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware entropy_src_smoke 3.000s 29.938us 1 1 100.00
entropy_src_rng 1.267m 15.102ms 1 1 100.00
entropy_src_fw_ov 1.100m 10.197ms 1 1 100.00
V2 firmware_mode entropy_src_fw_ov 1.100m 10.197ms 1 1 100.00
V2 rng_mode entropy_src_rng 1.267m 15.102ms 1 1 100.00
V2 rng_max_rate entropy_src_rng_max_rate 2.517m 15.202ms 1 1 100.00
V2 health_checks entropy_src_rng 1.267m 15.102ms 1 1 100.00
V2 conditioning entropy_src_rng 1.267m 15.102ms 1 1 100.00
V2 interrupts entropy_src_rng 1.267m 15.102ms 1 1 100.00
entropy_src_intr 20.000s 12.193ms 0 1 0.00
V2 alerts entropy_src_rng 1.267m 15.102ms 1 1 100.00
entropy_src_functional_alerts 8.000s 174.105us 1 1 100.00
V2 stress_all entropy_src_stress_all 47.000s 7.430ms 1 1 100.00
V2 functional_errors entropy_src_functional_errors 4.000s 40.262us 1 1 100.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 9.000s 258.251us 1 1 100.00
V2 intr_test entropy_src_intr_test 3.000s 31.745us 1 1 100.00
V2 alert_test entropy_src_alert_test 3.000s 55.385us 1 1 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 6.000s 239.026us 1 1 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 6.000s 239.026us 1 1 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 91.566us 1 1 100.00
entropy_src_csr_rw 4.000s 306.707us 1 1 100.00
entropy_src_csr_aliasing 5.000s 114.697us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 691.267us 1 1 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 91.566us 1 1 100.00
entropy_src_csr_rw 4.000s 306.707us 1 1 100.00
entropy_src_csr_aliasing 5.000s 114.697us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 691.267us 1 1 100.00
V2 TOTAL 11 12 91.67
V2S tl_intg_err entropy_src_sec_cm 4.000s 96.114us 1 1 100.00
entropy_src_tl_intg_err 5.000s 336.386us 1 1 100.00
V2S sec_cm_config_regwen entropy_src_rng 1.267m 15.102ms 1 1 100.00
entropy_src_cfg_regwen 3.000s 27.036us 1 1 100.00
V2S sec_cm_config_mubi entropy_src_rng 1.267m 15.102ms 1 1 100.00
V2S sec_cm_config_redun entropy_src_rng 1.267m 15.102ms 1 1 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 1.267m 15.102ms 1 1 100.00
entropy_src_fw_ov 1.100m 10.197ms 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 4.000s 40.262us 1 1 100.00
entropy_src_sec_cm 4.000s 96.114us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 4.000s 40.262us 1 1 100.00
entropy_src_sec_cm 4.000s 96.114us 1 1 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 1.267m 15.102ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 4.000s 40.262us 1 1 100.00
entropy_src_sec_cm 4.000s 96.114us 1 1 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 4.000s 40.262us 1 1 100.00
entropy_src_sec_cm 4.000s 96.114us 1 1 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 4.000s 40.262us 1 1 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 8.000s 174.105us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 5.000s 336.386us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 1.833m 17.241ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 21 22 95.45

Failure Buckets