HMAC Simulation Results

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: 72c264a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 6.550s 3.021ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.650s 71.197us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.910s 142.091us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.020s 4.045ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.170s 112.152us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.890s 205.946us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.910s 142.091us 1 1 100.00
hmac_csr_aliasing 2.170s 112.152us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 35.050s 17.839ms 1 1 100.00
V2 back_pressure hmac_back_pressure 9.360s 245.092us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.313m 31.597ms 1 1 100.00
hmac_test_sha384_vectors 18.770s 280.499us 1 1 100.00
hmac_test_sha512_vectors 6.160m 11.288ms 1 1 100.00
hmac_test_hmac256_vectors 8.460s 1.287ms 1 1 100.00
hmac_test_hmac384_vectors 7.800s 263.851us 1 1 100.00
hmac_test_hmac512_vectors 7.600s 1.144ms 1 1 100.00
V2 burst_wr hmac_burst_wr 18.200s 7.256ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 3.675m 1.889ms 1 1 100.00
V2 error hmac_error 11.990s 325.527us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.178m 22.968ms 1 1 100.00
V2 save_and_restore hmac_smoke 6.550s 3.021ms 1 1 100.00
hmac_long_msg 35.050s 17.839ms 1 1 100.00
hmac_back_pressure 9.360s 245.092us 1 1 100.00
hmac_datapath_stress 3.675m 1.889ms 1 1 100.00
hmac_burst_wr 18.200s 7.256ms 1 1 100.00
hmac_stress_all 3.665m 28.413ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 6.550s 3.021ms 1 1 100.00
hmac_long_msg 35.050s 17.839ms 1 1 100.00
hmac_back_pressure 9.360s 245.092us 1 1 100.00
hmac_datapath_stress 3.675m 1.889ms 1 1 100.00
hmac_wipe_secret 1.178m 22.968ms 1 1 100.00
hmac_test_sha256_vectors 3.313m 31.597ms 1 1 100.00
hmac_test_sha384_vectors 18.770s 280.499us 1 1 100.00
hmac_test_sha512_vectors 6.160m 11.288ms 1 1 100.00
hmac_test_hmac256_vectors 8.460s 1.287ms 1 1 100.00
hmac_test_hmac384_vectors 7.800s 263.851us 1 1 100.00
hmac_test_hmac512_vectors 7.600s 1.144ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 6.550s 3.021ms 1 1 100.00
hmac_long_msg 35.050s 17.839ms 1 1 100.00
hmac_back_pressure 9.360s 245.092us 1 1 100.00
hmac_datapath_stress 3.675m 1.889ms 1 1 100.00
hmac_burst_wr 18.200s 7.256ms 1 1 100.00
hmac_error 11.990s 325.527us 1 1 100.00
hmac_wipe_secret 1.178m 22.968ms 1 1 100.00
hmac_test_sha256_vectors 3.313m 31.597ms 1 1 100.00
hmac_test_sha384_vectors 18.770s 280.499us 1 1 100.00
hmac_test_sha512_vectors 6.160m 11.288ms 1 1 100.00
hmac_test_hmac256_vectors 8.460s 1.287ms 1 1 100.00
hmac_test_hmac384_vectors 7.800s 263.851us 1 1 100.00
hmac_test_hmac512_vectors 7.600s 1.144ms 1 1 100.00
hmac_stress_all 3.665m 28.413ms 1 1 100.00
V2 stress_all hmac_stress_all 3.665m 28.413ms 1 1 100.00
V2 alert_test hmac_alert_test 0.600s 16.436us 1 1 100.00
V2 intr_test hmac_intr_test 0.570s 34.008us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.300s 604.255us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.300s 604.255us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.650s 71.197us 1 1 100.00
hmac_csr_rw 0.910s 142.091us 1 1 100.00
hmac_csr_aliasing 2.170s 112.152us 1 1 100.00
hmac_same_csr_outstanding 1.860s 240.401us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.650s 71.197us 1 1 100.00
hmac_csr_rw 0.910s 142.091us 1 1 100.00
hmac_csr_aliasing 2.170s 112.152us 1 1 100.00
hmac_same_csr_outstanding 1.860s 240.401us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.740s 58.452us 1 1 100.00
hmac_tl_intg_err 1.480s 335.901us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.480s 335.901us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 6.550s 3.021ms 1 1 100.00
V3 stress_reset hmac_stress_reset 1.260s 58.469us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.881m 2.761ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.610s 100.980us 1 1 100.00
TOTAL 28 28 100.00