I2C Simulation Results

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: 72c264a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	42.510s	4.967ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	17.870s	1.600ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.820s	43.570us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.790s	65.557us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.110s	221.112us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.350s	122.579us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.070s	114.401us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.790s	65.557us	1	1	100.00
		i2c_csr_aliasing	1.350s	122.579us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.690s	35.795us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	1.425m	22.568ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	11.850s	1.124ms	1	1	100.00
V2	host_override	i2c_host_override	0.780s	87.662us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.404m	19.243ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.643m	4.382ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.170s	195.726us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.310s	361.021us	1	1	100.00
		i2c_host_fifo_reset_rx	2.920s	2.737ms	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	56.450s	11.857ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	16.570s	537.346us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.740s	28.311us	0	1	0.00
V2	target_glitch	i2c_target_glitch	3.220s	1.804ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	26.040s	7.684ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.190s	12.611ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	12.390s	2.084ms	1	1	100.00
		i2c_target_intr_smoke	6.140s	976.956us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.230s	826.365us	1	1	100.00
		i2c_target_fifo_reset_tx	0.930s	816.782us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	5.320s	14.235ms	1	1	100.00
		i2c_target_stress_rd	12.390s	2.084ms	1	1	100.00
		i2c_target_intr_stress_wr	3.460s	4.725ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.630s	1.318ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	24.680s	2.568ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.210s	3.401ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.270s	402.939us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.020s	1.603ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.320s	177.455us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	11.850s	1.124ms	1	1	100.00
		i2c_host_perf_precise	2.100s	225.521us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	16.570s	537.346us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.390s	428.527us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.890s	2.317ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.050s	572.198us	1	1	100.00
		i2c_target_nack_txstretch	1.040s	143.707us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.740s	3.271ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.650s	865.991us	1	1	100.00
V2	alert_test	i2c_alert_test	0.610s	46.238us	1	1	100.00
V2	intr_test	i2c_intr_test	0.750s	40.196us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.430s	107.509us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.430s	107.509us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.820s	43.570us	1	1	100.00
		i2c_csr_rw	0.790s	65.557us	1	1	100.00
		i2c_csr_aliasing	1.350s	122.579us	1	1	100.00
		i2c_same_csr_outstanding	1.270s	27.474us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.820s	43.570us	1	1	100.00
		i2c_csr_rw	0.790s	65.557us	1	1	100.00
		i2c_csr_aliasing	1.350s	122.579us	1	1	100.00
		i2c_same_csr_outstanding	1.270s	27.474us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.590s	167.845us	1	1	100.00
		i2c_sec_cm	0.920s	801.935us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.590s	167.845us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	8.570s	500.421us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.260s	107.192us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.210s	2.356ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 4 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.82252177180467475329706621310634684573026053492950131622548316961133989873909
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  35794963 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  35794963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.109047905462003716307469097390020390857469969527484335158599717839655069137590
      Line 115, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 22568119511 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 22568119511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.67245958697615310055630191423859604125440758346311141979530776532404991524576
      Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2356172286 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 2356172286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.90947233641674218695911909487243387896872837727914810900343049402555366692831
      Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  28310617 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  28310617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.17375622247292944421116162243835433581744981828780997909276863947418199150628
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1803936077 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1803936077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.6738093581335299445183292579523439730344511403676608311810973786725656912585
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 107191865 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 248 [0xf8])
        UVM_INFO @ 107191865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.56478317940934758505902478708742004833289944013068542550924498800022619388944
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 500421180 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 500421180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---