KEYMGR Simulation Results

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: 72c264a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 1.690s 46.205us 1 1 100.00
V1 random keymgr_random 3.800s 124.359us 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.100s 199.858us 1 1 100.00
V1 csr_rw keymgr_csr_rw 0.920s 37.421us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 9.530s 252.319us 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 3.510s 796.275us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.330s 75.963us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 0.920s 37.421us 1 1 100.00
keymgr_csr_aliasing 3.510s 796.275us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 7.080s 188.670us 1 1 100.00
V2 sideload keymgr_sideload 2.360s 298.778us 1 1 100.00
keymgr_sideload_kmac 5.910s 798.911us 1 1 100.00
keymgr_sideload_aes 3.070s 114.319us 1 1 100.00
keymgr_sideload_otbn 1.340s 77.077us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 3.610s 116.979us 1 1 100.00
V2 lc_disable keymgr_lc_disable 1.930s 107.307us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 4.450s 2.660ms 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 2.660s 300.266us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 13.460s 3.467ms 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 2.510s 75.741us 1 1 100.00
V2 stress_all keymgr_stress_all 5.320s 301.596us 1 1 100.00
V2 intr_test keymgr_intr_test 0.760s 41.076us 1 1 100.00
V2 alert_test keymgr_alert_test 0.720s 35.999us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 3.560s 544.219us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 3.560s 544.219us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.100s 199.858us 1 1 100.00
keymgr_csr_rw 0.920s 37.421us 1 1 100.00
keymgr_csr_aliasing 3.510s 796.275us 1 1 100.00
keymgr_same_csr_outstanding 2.200s 318.371us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.100s 199.858us 1 1 100.00
keymgr_csr_rw 0.920s 37.421us 1 1 100.00
keymgr_csr_aliasing 3.510s 796.275us 1 1 100.00
keymgr_same_csr_outstanding 2.200s 318.371us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 4.880s 1.578ms 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 4.880s 1.578ms 1 1 100.00
keymgr_tl_intg_err 4.790s 283.744us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 1.470s 125.732us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 1.470s 125.732us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 1.470s 125.732us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 1.470s 125.732us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 3.630s 362.863us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 4.880s 1.578ms 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 4.880s 1.578ms 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 4.790s 283.744us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 1.470s 125.732us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 7.080s 188.670us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 3.800s 124.359us 1 1 100.00
keymgr_csr_rw 0.920s 37.421us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 3.800s 124.359us 1 1 100.00
keymgr_csr_rw 0.920s 37.421us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 3.800s 124.359us 1 1 100.00
keymgr_csr_rw 0.920s 37.421us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 1.930s 107.307us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 13.460s 3.467ms 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 13.460s 3.467ms 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 3.800s 124.359us 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 2.190s 175.732us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 4.880s 1.578ms 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 4.880s 1.578ms 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 4.880s 1.578ms 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 2.130s 458.874us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 1.930s 107.307us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 4.880s 1.578ms 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 4.880s 1.578ms 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 4.880s 1.578ms 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 2.130s 458.874us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 2.130s 458.874us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 4.880s 1.578ms 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 2.130s 458.874us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 4.880s 1.578ms 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 2.130s 458.874us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 5.760s 497.436us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00