| V1 |
smoke |
keymgr_dpe_smoke |
15.700s |
861.281us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.070s |
116.612us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
0.940s |
53.316us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
12.130s |
2.365ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
2.480s |
47.140us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.490s |
81.918us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
0.940s |
53.316us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.480s |
47.140us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
0.830s |
15.045us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
0.780s |
22.702us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
1.780s |
75.943us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
1.780s |
75.943us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.070s |
116.612us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.940s |
53.316us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.480s |
47.140us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.720s |
455.971us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.070s |
116.612us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.940s |
53.316us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.480s |
47.140us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.720s |
455.971us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
6.320s |
1.680ms |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
3.120s |
169.409us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
2.320s |
215.390us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
2.320s |
215.390us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
2.320s |
215.390us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
2.320s |
215.390us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
3.490s |
749.364us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
6.320s |
1.680ms |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
6.320s |
1.680ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |