| V1 |
smoke |
kmac_smoke |
3.000s |
616.110us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
0.790s |
57.390us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
0.970s |
62.188us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
5.820s |
291.962us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
6.410s |
452.937us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
1.860s |
119.156us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
0.970s |
62.188us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
6.410s |
452.937us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.660s |
14.213us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.140s |
29.298us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
26.716m |
51.348ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
3.672m |
6.648ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
34.390s |
2.135ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
30.280s |
2.319ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
21.760s |
3.212ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
14.520s |
1.720ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
3.169m |
58.922ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
1.646m |
23.179ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.590s |
91.645us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
3.720s |
103.474us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
40.590s |
777.599us |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
2.460m |
3.418ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
4.978m |
20.939ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
38.550s |
3.096ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
2.856m |
5.549ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
1.540s |
413.549us |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
5.800s |
433.923us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
1.150s |
83.426us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
0.950s |
42.258us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
32.560s |
4.088ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
2.000s |
196.143us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
31.762m |
214.176ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.700s |
38.100us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
0.920s |
84.376us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
1.800s |
78.508us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
1.800s |
78.508us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
0.790s |
57.390us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
0.970s |
62.188us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
6.410s |
452.937us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.840s |
76.084us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
0.790s |
57.390us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
0.970s |
62.188us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
6.410s |
452.937us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.840s |
76.084us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.000s |
217.089us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.000s |
217.089us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.000s |
217.089us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.000s |
217.089us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
2.140s |
120.001us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
1.674m |
14.075ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
1.840s |
185.546us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
1.840s |
185.546us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
2.000s |
196.143us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
3.000s |
616.110us |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
40.590s |
777.599us |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.000s |
217.089us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
1.674m |
14.075ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
1.674m |
14.075ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
1.674m |
14.075ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
3.000s |
616.110us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
2.000s |
196.143us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
1.674m |
14.075ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
55.150s |
2.827ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
3.000s |
616.110us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
1.202m |
2.771ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |