72c264a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 41.000s | 2.593ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 3.000s | 16.903us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 3.000s | 46.348us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 87.660us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 2.000s | 17.413us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 3.000s | 41.150us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 3.000s | 46.348us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 2.000s | 17.413us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | mbx_stress | mbx_stress | 4.000s | 245.760us | 0 | 1 | 0.00 |
| V2 | mbx_max_activity | mbx_stress_zero_delays | 2.000s | 17.376us | 0 | 1 | 0.00 |
| V2 | mbx_imbx_oob | mbx_imbx_oob | 4.000s | 288.380us | 0 | 1 | 0.00 |
| V2 | mbx_doe_intr_msg | mbx_doe_intr_msg | 11.000s | 1.410ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 3.000s | 66.649us | 1 | 1 | 100.00 |
| V2 | intr_test | mbx_intr_test | 3.000s | 44.641us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 5.000s | 179.056us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 5.000s | 179.056us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 3.000s | 16.903us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 46.348us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 2.000s | 17.413us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 28.040us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 3.000s | 16.903us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 46.348us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 2.000s | 17.413us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 28.040us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 8 | 62.50 | |||
| V2S | tl_intg_err | mbx_tl_intg_err | 3.000s | 492.207us | 1 | 1 | 100.00 |
| mbx_sec_cm | 3.000s | 138.124us | 1 | 1 | 100.00 | ||
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| TOTAL | 13 | 16 | 81.25 |
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 2 failures:
Test mbx_stress_zero_delays has 1 failures.
0.mbx_stress_zero_delays.65451051256653092759365634428549477481954504151344932209997058966677946765827
Line 86, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log
UVM_ERROR @ 17376418 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 17376418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_imbx_oob has 1 failures.
0.mbx_imbx_oob.68649527769900239502318173044609469772324227091514692684155702957748903089549
Line 90, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log
UVM_ERROR @ 288380165 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 288380165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched has 1 failures:
0.mbx_stress.65591675214836162211962476074631382275363922758212294822971698369327791530291
Line 144, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log
UVM_ERROR @ 245759702 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (2954621915 [0xb01bf3db] vs 0 [0x0]) RDATA read data mismatched
UVM_INFO @ 245759702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---