OTBN Simulation Results

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: 72c264a

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	49.149us	1	1	100.00
V1	single_binary	otbn_single	13.000s	521.243us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	20.574us	1	1	100.00
V1	csr_rw	otbn_csr_rw	4.000s	101.639us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	6.000s	65.757us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	20.380us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	6.000s	36.081us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	4.000s	101.639us	1	1	100.00
		otbn_csr_aliasing	5.000s	20.380us	1	1	100.00
V1	mem_walk	otbn_mem_walk	13.000s	283.653us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	13.000s	241.408us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	17.000s	121.070us	1	1	100.00
V2	multi_error	otbn_multi_err	41.000s	329.111us	1	1	100.00
V2	back_to_back	otbn_multi	53.000s	228.028us	1	1	100.00
V2	stress_all	otbn_stress_all	29.000s	520.582us	1	1	100.00
V2	lc_escalation	otbn_escalate	7.000s	18.912us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	6.000s	27.265us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	6.000s	25.212us	1	1	100.00
V2	alert_test	otbn_alert_test	5.000s	19.244us	1	1	100.00
V2	intr_test	otbn_intr_test	5.000s	14.735us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	86.834us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	86.834us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	20.574us	1	1	100.00
		otbn_csr_rw	4.000s	101.639us	1	1	100.00
		otbn_csr_aliasing	5.000s	20.380us	1	1	100.00
		otbn_same_csr_outstanding	4.000s	20.795us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	20.574us	1	1	100.00
		otbn_csr_rw	4.000s	101.639us	1	1	100.00
		otbn_csr_aliasing	5.000s	20.380us	1	1	100.00
		otbn_same_csr_outstanding	4.000s	20.795us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	7.000s	34.267us	1	1	100.00
		otbn_dmem_err	15.000s	48.981us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	8.000s	200.646us	1	1	100.00
		otbn_controller_ispr_rdata_err	10.000s	69.489us	1	1	100.00
		otbn_mac_bignum_acc_err	7.000s	103.613us	1	1	100.00
		otbn_urnd_err	7.000s	15.369us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	6.000s	29.270us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	6.000s	35.023us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	5.000s	66.320us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	4.200m	1.780ms	1	1	100.00
		otbn_tl_intg_err	10.000s	257.070us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	12.000s	355.050us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	4.200m	1.780ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	4.200m	1.780ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	49.149us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	15.000s	48.981us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	7.000s	34.267us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	10.000s	257.070us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	7.000s	18.912us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	7.000s	34.267us	1	1	100.00
		otbn_dmem_err	15.000s	48.981us	1	1	100.00
		otbn_zero_state_err_urnd	6.000s	27.265us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	29.270us	1	1	100.00
		otbn_sec_cm	4.200m	1.780ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.200m	1.780ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	13.000s	521.243us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	7.000s	34.267us	1	1	100.00
		otbn_dmem_err	15.000s	48.981us	1	1	100.00
		otbn_zero_state_err_urnd	6.000s	27.265us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	29.270us	1	1	100.00
		otbn_sec_cm	4.200m	1.780ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.200m	1.780ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	7.000s	18.912us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	7.000s	34.267us	1	1	100.00
		otbn_dmem_err	15.000s	48.981us	1	1	100.00
		otbn_zero_state_err_urnd	6.000s	27.265us	1	1	100.00
		otbn_illegal_mem_acc	6.000s	29.270us	1	1	100.00
		otbn_sec_cm	4.200m	1.780ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.200m	1.780ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	13.000s	521.243us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	5.000s	23.533us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	6.000s	134.388us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	56.000s	469.189us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	56.000s	469.189us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	8.000s	64.572us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.200m	1.780ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.200m	1.780ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	7.000s	200.279us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.200m	1.780ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.200m	1.780ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	7.000s	73.247us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	7.000s	73.247us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	5.000s	59.559us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	13.000s	521.243us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	13.000s	521.243us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	13.000s	521.243us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	53.000s	228.028us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	13.000s	521.243us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	13.000s	521.243us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	25.200us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	13.000s	521.243us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.200m	1.780ms	1	1	100.00
V2S		TOTAL			20	20	100.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	57.000s	305.128us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			40	41	97.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:946) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.104574564531733446427979810734171008954229091709933964016041933165846909867982
      Line 179, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 305128109 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 305128109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---