ROM_CTRL/32KB Simulation Results

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: 72c264a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.440s 423.927us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.810s 2.112ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.270s 170.431us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 3.970s 961.308us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 3.780s 517.708us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.230s 663.084us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.270s 170.431us 1 1 100.00
rom_ctrl_csr_aliasing 3.780s 517.708us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.470s 374.779us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.830s 2.113ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.950s 621.196us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 10.240s 1.484ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.520s 566.918us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 3.550s 127.939us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.610s 482.679us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.610s 482.679us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.810s 2.112ms 1 1 100.00
rom_ctrl_csr_rw 4.270s 170.431us 1 1 100.00
rom_ctrl_csr_aliasing 3.780s 517.708us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.710s 186.715us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.810s 2.112ms 1 1 100.00
rom_ctrl_csr_rw 4.270s 170.431us 1 1 100.00
rom_ctrl_csr_aliasing 3.780s 517.708us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.710s 186.715us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.002m 1.561ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 20.030s 8.740ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.561m 374.071us 1 1 100.00
rom_ctrl_tl_intg_err 43.120s 344.247us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.561m 374.071us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.561m 374.071us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.002m 1.561ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.002m 1.561ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.002m 1.561ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.002m 1.561ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.002m 1.561ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.561m 374.071us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.561m 374.071us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.440s 423.927us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.440s 423.927us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.440s 423.927us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 43.120s 344.247us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.002m 1.561ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.520s 566.918us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.002m 1.561ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.002m 1.561ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.002m 1.561ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 20.030s 8.740ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.561m 374.071us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.157m 28.892ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00