ROM_CTRL/64KB Simulation Results

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: 72c264a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 10.510s 2.075ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.610s 305.322us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 9.000s 383.488us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.170s 3.128ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.390s 1.029ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 9.340s 1.033ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 9.000s 383.488us 1 1 100.00
rom_ctrl_csr_aliasing 7.390s 1.029ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 8.090s 296.197us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.570s 1.165ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.610s 312.670us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 22.000s 826.107us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.540s 556.185us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.140s 205.327us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.660s 212.608us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.660s 212.608us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.610s 305.322us 1 1 100.00
rom_ctrl_csr_rw 9.000s 383.488us 1 1 100.00
rom_ctrl_csr_aliasing 7.390s 1.029ms 1 1 100.00
rom_ctrl_same_csr_outstanding 8.180s 564.163us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.610s 305.322us 1 1 100.00
rom_ctrl_csr_rw 9.000s 383.488us 1 1 100.00
rom_ctrl_csr_aliasing 7.390s 1.029ms 1 1 100.00
rom_ctrl_same_csr_outstanding 8.180s 564.163us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.751m 25.306ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 33.610s 1.129ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 6.975m 1.413ms 1 1 100.00
rom_ctrl_tl_intg_err 1.465m 695.558us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 6.975m 1.413ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 6.975m 1.413ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.751m 25.306ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.751m 25.306ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.751m 25.306ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.751m 25.306ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.751m 25.306ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 6.975m 1.413ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 6.975m 1.413ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 10.510s 2.075ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 10.510s 2.075ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 10.510s 2.075ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.465m 695.558us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.751m 25.306ms 1 1 100.00
rom_ctrl_kmac_err_chk 14.540s 556.185us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.751m 25.306ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.751m 25.306ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.751m 25.306ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 33.610s 1.129ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 6.975m 1.413ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 53.130s 1.477ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00