SPI_DEVICE/1R1W Simulation Results

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: 72c264a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	21.760s	6.395ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.240s	74.831us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.240s	124.263us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	21.590s	551.803us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.090s	321.430us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.660s	107.049us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.240s	124.263us	1	1	100.00
		spi_device_csr_aliasing	6.090s	321.430us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.830s	10.441us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.470s	41.201us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.940s	19.298us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.800s	1.863us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.820s	5.855us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.240s	60.976us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.240s	60.976us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.130s	2.374ms	1	1	100.00
		spi_device_tpm_sts_read	1.140s	45.304us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	29.200s	30.386ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.200s	1.454ms	1	1	100.00
		spi_device_flash_all	1.339m	127.724ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	11.820s	83.506ms	1	1	100.00
		spi_device_flash_all	1.339m	127.724ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	11.820s	83.506ms	1	1	100.00
		spi_device_flash_all	1.339m	127.724ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.339m	127.724ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	16.320s	4.118ms	1	1	100.00
		spi_device_flash_all	1.339m	127.724ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	16.320s	4.118ms	1	1	100.00
		spi_device_flash_all	1.339m	127.724ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	16.320s	4.118ms	1	1	100.00
		spi_device_flash_all	1.339m	127.724ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	16.320s	4.118ms	1	1	100.00
		spi_device_flash_all	1.339m	127.724ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	16.320s	4.118ms	1	1	100.00
		spi_device_flash_all	1.339m	127.724ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	1.790s	36.899us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	18.080s	6.557ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	18.080s	6.557ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	18.080s	6.557ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.300s	44.975us	1	1	100.00
		spi_device_read_buffer_direct	3.100s	125.656us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	18.080s	6.557ms	1	1	100.00
		spi_device_flash_all	1.339m	127.724ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.339m	127.724ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.339m	127.724ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.330s	870.061us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.330s	870.061us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	21.760s	6.395ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	55.690s	6.045ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.488m	27.964ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.980s	34.713us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.880s	15.813us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.150s	625.399us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.150s	625.399us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.240s	74.831us	1	1	100.00
		spi_device_csr_rw	1.240s	124.263us	1	1	100.00
		spi_device_csr_aliasing	6.090s	321.430us	1	1	100.00
		spi_device_same_csr_outstanding	3.210s	61.081us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.240s	74.831us	1	1	100.00
		spi_device_csr_rw	1.240s	124.263us	1	1	100.00
		spi_device_csr_aliasing	6.090s	321.430us	1	1	100.00
		spi_device_same_csr_outstanding	3.210s	61.081us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.170s	48.967us	1	1	100.00
		spi_device_tl_intg_err	10.240s	12.248ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.240s	12.248ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.051m	20.275ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.57599500359737850633008440771476367794489598160904719973973798522628624879193
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1462582 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[46])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1462582 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1462582 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[942])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.66268572590739781733259538657720204663809882672549824719436536091321734861600
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3352758 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x687bb9 [11010000111101110111001] vs 0x0 [0])
        UVM_ERROR @   3418758 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe52aca [111001010010101011001010] vs 0x0 [0])
        UVM_ERROR @   3471758 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbd2f65 [101111010010111101100101] vs 0x0 [0])
        UVM_ERROR @   3564758 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4dde94 [10011011101111010010100] vs 0x0 [0])
        UVM_ERROR @   3626758 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5b22c1 [10110110010001011000001] vs 0x0 [0])