| V1 |
smoke |
spi_host_smoke |
4.183m |
39.104ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
spi_host_csr_hw_reset |
2.000s |
21.462us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
spi_host_csr_rw |
2.000s |
39.163us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
spi_host_csr_bit_bash |
4.000s |
65.300us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
spi_host_csr_aliasing |
2.000s |
23.411us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
spi_host_csr_mem_rw_with_rand_reset |
3.000s |
63.503us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
spi_host_csr_rw |
2.000s |
39.163us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
2.000s |
23.411us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
spi_host_mem_walk |
2.000s |
22.046us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
spi_host_mem_partial_access |
2.000s |
22.255us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
performance |
spi_host_performance |
6.000s |
23.150us |
1 |
1 |
100.00 |
| V2 |
error_event_intr |
spi_host_overflow_underflow |
8.000s |
331.131us |
1 |
1 |
100.00 |
|
|
spi_host_error_cmd |
4.000s |
18.168us |
1 |
1 |
100.00 |
|
|
spi_host_event |
8.000s |
366.333us |
1 |
1 |
100.00 |
| V2 |
clock_rate |
spi_host_speed |
9.000s |
369.541us |
1 |
1 |
100.00 |
| V2 |
speed |
spi_host_speed |
9.000s |
369.541us |
1 |
1 |
100.00 |
| V2 |
chip_select_timing |
spi_host_speed |
9.000s |
369.541us |
1 |
1 |
100.00 |
| V2 |
sw_reset |
spi_host_sw_reset |
7.000s |
57.955us |
1 |
1 |
100.00 |
| V2 |
passthrough_mode |
spi_host_passthrough_mode |
4.000s |
64.809us |
1 |
1 |
100.00 |
| V2 |
cpol_cpha |
spi_host_speed |
9.000s |
369.541us |
1 |
1 |
100.00 |
| V2 |
full_cycle |
spi_host_speed |
9.000s |
369.541us |
1 |
1 |
100.00 |
| V2 |
duplex |
spi_host_smoke |
4.183m |
39.104ms |
1 |
1 |
100.00 |
| V2 |
tx_rx_only |
spi_host_smoke |
4.183m |
39.104ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
spi_host_stress_all |
23.000s |
2.929ms |
1 |
1 |
100.00 |
| V2 |
spien |
spi_host_spien |
6.000s |
1.569ms |
1 |
1 |
100.00 |
| V2 |
stall |
spi_host_status_stall |
11.000s |
1.180ms |
1 |
1 |
100.00 |
| V2 |
Idlecsbactive |
spi_host_idlecsbactive |
3.000s |
377.910us |
1 |
1 |
100.00 |
| V2 |
data_fifo_status |
spi_host_overflow_underflow |
8.000s |
331.131us |
1 |
1 |
100.00 |
| V2 |
alert_test |
spi_host_alert_test |
3.000s |
23.966us |
1 |
1 |
100.00 |
| V2 |
intr_test |
spi_host_intr_test |
2.000s |
19.701us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
spi_host_tl_errors |
3.000s |
115.141us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
spi_host_tl_errors |
3.000s |
115.141us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
spi_host_csr_hw_reset |
2.000s |
21.462us |
1 |
1 |
100.00 |
|
|
spi_host_csr_rw |
2.000s |
39.163us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
2.000s |
23.411us |
1 |
1 |
100.00 |
|
|
spi_host_same_csr_outstanding |
3.000s |
105.712us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
spi_host_csr_hw_reset |
2.000s |
21.462us |
1 |
1 |
100.00 |
|
|
spi_host_csr_rw |
2.000s |
39.163us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
2.000s |
23.411us |
1 |
1 |
100.00 |
|
|
spi_host_same_csr_outstanding |
3.000s |
105.712us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
15 |
15 |
100.00 |
| V2S |
tl_intg_err |
spi_host_tl_intg_err |
2.000s |
50.961us |
1 |
1 |
100.00 |
|
|
spi_host_sec_cm |
3.000s |
47.385us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
spi_host_tl_intg_err |
2.000s |
50.961us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
spi_host_upper_range_clkdiv |
39.000s |
767.505us |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
26 |
26 |
100.00 |