SRAM_CTRL/MAIN Simulation Results

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: 72c264a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	55.900s	1.280ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.810s	19.006us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.660s	12.722us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.120s	134.114us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	74.542us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.580s	1.281ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.660s	12.722us	1	1	100.00
		sram_ctrl_csr_aliasing	0.730s	74.542us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.848m	55.299ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.123m	2.782ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.922m	36.457ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.082m	20.519ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	9.385m	43.884ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.080m	45.688ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	28.170s	12.367ms	1	1	100.00
V2	executable	sram_ctrl_executable	6.027m	16.936ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	7.560s	3.044ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.912m	12.067ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	4.210s	704.493us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.530s	876.068us	1	1	100.00
		sram_ctrl_throughput_w_readback	46.880s	1.710ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.366m	5.081ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.350s	720.392us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	55.094m	942.856ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.780s	53.022us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.990s	79.171us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.990s	79.171us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.810s	19.006us	1	1	100.00
		sram_ctrl_csr_rw	0.660s	12.722us	1	1	100.00
		sram_ctrl_csr_aliasing	0.730s	74.542us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.910s	23.499us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.810s	19.006us	1	1	100.00
		sram_ctrl_csr_rw	0.660s	12.722us	1	1	100.00
		sram_ctrl_csr_aliasing	0.730s	74.542us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.910s	23.499us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	42.430s	14.676ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.780s	2.773us	0	1	0.00
		sram_ctrl_tl_intg_err	1.360s	1.350ms	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.780s	2.773us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.360s	1.350ms	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.366m	5.081ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.366m	5.081ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.660s	12.722us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.027m	16.936ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.027m	16.936ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.027m	16.936ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	28.170s	12.367ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.840s	683.106us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	42.430s	14.676ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.800s	2.862ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	55.900s	1.280ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	55.900s	1.280ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.027m	16.936ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.780s	2.773us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	28.170s	12.367ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.780s	2.773us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.780s	2.773us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	55.900s	1.280ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.780s	2.773us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	16.810s	13.381ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.74714156881308984285356596311637782613673840073125903994930299714165100486873
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   2772916 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   2772916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---