SRAM_CTRL/RET Simulation Results

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: 72c264a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.150s	373.446us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	57.266us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.910s	44.735us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.520s	155.057us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	15.613us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.880s	44.039us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.910s	44.735us	1	1	100.00
		sram_ctrl_csr_aliasing	0.740s	15.613us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.670s	96.413us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.860s	299.994us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.974m	1.920ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.941m	11.332ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	45.930s	8.017ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	12.352m	3.787ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.230s	529.735us	1	1	100.00
V2	executable	sram_ctrl_executable	9.152m	50.672ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	2.860s	260.616us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.759m	11.780ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	9.280s	83.134us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	8.480s	82.529us	1	1	100.00
		sram_ctrl_throughput_w_readback	19.540s	194.399us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.704m	7.974ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.760s	94.246us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	27.168m	36.631ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.720s	23.000us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.110s	417.434us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.110s	417.434us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	57.266us	1	1	100.00
		sram_ctrl_csr_rw	0.910s	44.735us	1	1	100.00
		sram_ctrl_csr_aliasing	0.740s	15.613us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.660s	15.474us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	57.266us	1	1	100.00
		sram_ctrl_csr_rw	0.910s	44.735us	1	1	100.00
		sram_ctrl_csr_aliasing	0.740s	15.613us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.660s	15.474us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.630s	1.512ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.610s	6.503us	0	1	0.00
		sram_ctrl_tl_intg_err	1.300s	112.661us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.610s	6.503us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.300s	112.661us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.704m	7.974ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.704m	7.974ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.910s	44.735us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	9.152m	50.672ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	9.152m	50.672ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	9.152m	50.672ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.230s	529.735us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.020s	173.130us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.630s	1.512ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.830s	29.055us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.150s	373.446us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.150s	373.446us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	9.152m	50.672ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.610s	6.503us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.230s	529.735us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.610s	6.503us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.610s	6.503us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.150s	373.446us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.610s	6.503us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.427m	8.951ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.60462974647627399263649251988521867395001216980796719757317341823205034359765
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6502747 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6502747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---