UART Simulation Results

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: 72c264a

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.630s	489.254us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.770s	31.926us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.700s	43.477us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.930s	179.913us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.640s	77.357us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.770s	17.381us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.700s	43.477us	1	1	100.00
		uart_csr_aliasing	0.640s	77.357us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	7.020s	11.142ms	1	1	100.00
V2	parity	uart_smoke	1.630s	489.254us	1	1	100.00
		uart_tx_rx	7.020s	11.142ms	1	1	100.00
V2	parity_error	uart_intr	10.410s	29.431ms	1	1	100.00
		uart_rx_parity_err	29.330s	72.113ms	1	1	100.00
V2	watermark	uart_tx_rx	7.020s	11.142ms	1	1	100.00
		uart_intr	10.410s	29.431ms	1	1	100.00
V2	fifo_full	uart_fifo_full	19.520s	52.958ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	9.010s	32.072ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	2.313m	251.295ms	1	1	100.00
V2	rx_frame_err	uart_intr	10.410s	29.431ms	1	1	100.00
V2	rx_break_err	uart_intr	10.410s	29.431ms	1	1	100.00
V2	rx_timeout	uart_intr	10.410s	29.431ms	1	1	100.00
V2	perf	uart_perf	1.706m	14.101ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.540s	966.143us	1	1	100.00
V2	line_loopback	uart_loopback	2.540s	966.143us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.318m	46.052ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.140s	631.354us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	12.510s	6.977ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	21.520s	6.588ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	59.690s	86.972ms	1	1	100.00
V2	stress_all	uart_stress_all	1.063m	199.885ms	1	1	100.00
V2	alert_test	uart_alert_test	0.740s	43.889us	1	1	100.00
V2	intr_test	uart_intr_test	0.760s	65.042us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.990s	150.216us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.990s	150.216us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.770s	31.926us	1	1	100.00
		uart_csr_rw	0.700s	43.477us	1	1	100.00
		uart_csr_aliasing	0.640s	77.357us	1	1	100.00
		uart_same_csr_outstanding	0.900s	54.526us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.770s	31.926us	1	1	100.00
		uart_csr_rw	0.700s	43.477us	1	1	100.00
		uart_csr_aliasing	0.640s	77.357us	1	1	100.00
		uart_same_csr_outstanding	0.900s	54.526us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.040s	531.913us	1	1	100.00
		uart_tl_intg_err	1.250s	381.003us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.250s	381.003us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	21.530s	2.400ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.22552622254102208496823753045775612958923464977978510613477492671206766353835
      Line 77, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 44194735998 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 44205595998 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 44205645998 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 44205795998 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 44212825998 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0