CHIP Simulation Results

Thursday September 04 2025 16:03:40 UTC

GitHub Revision: `72c264a`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.006m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.006m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.661m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.635m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.876m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.424m	5.220ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.424m	5.220ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.424m	5.220ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	31.140s	10.200us	0	1	0.00
		chip_sw_example_manufacturer	2.367m		0	1	0.00
		chip_sw_example_concurrency	3.717m	4.511ms	1	1	100.00
		chip_sw_uart_smoketest_signed	13.623s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.840s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.200s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.200s		0	1	0.00
V1	xbar_smoke	xbar_smoke	18.840s	57.708us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.968m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.447m	8.784ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.436m	3.999ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.148m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	35.595s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.759m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.268m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.690s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.690s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.373m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.185m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.270m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.270m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.367m	3.737ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.523m	3.358ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.987m	13.677ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.651s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.662s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	21.499m	31.881ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.485m	4.409ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	24.344m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	24.344m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.121s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.244m	4.081ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.244m	4.081ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.680m	18.027ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.688m	5.596ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.166m	5.678ms	1	1	100.00
		chip_sw_aes_idle	3.770m	4.885ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.049m	4.468ms	1	1	100.00
		chip_sw_kmac_idle	3.451m	4.511ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	14.867m	11.820ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	13.960m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	14.706m	11.837ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	14.970m	12.018ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	12.369s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.009s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.935s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.583s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.190s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.777s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.483s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.369s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.009s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.935s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.583s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.190s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.777s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.483s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.269s		0	1	0.00
		chip_sw_aes_enc_jitter_en	36.210s	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	44.550s	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	43.480s	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	38.570s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.858s		0	1	0.00
		chip_sw_clkmgr_jitter	4.188m	4.660ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.477m	4.642ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	11.616s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	39.580s	10.280us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	37.260s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	38.200s	10.180us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	36.820s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	41.540s	10.100us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	14.032s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	14.521s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	14.147s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.323s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	20.084m	14.540ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	11.622m	13.941ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.244m	4.081ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.505s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	11.622m	13.941ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	19.103s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.826s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	14.299s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	22.699s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.867s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	20.084m	14.540ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.987m	13.677ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	24.913m	20.019ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.761m	9.581ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	9.077m	9.086ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.201m	4.678ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	20.084m	14.540ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	14.745s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	13.047s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	20.084m	14.540ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.321s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	9.077m	9.086ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.893s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	13.485s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.495s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.378s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.454s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	17.070s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	13.047s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	15.434s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	17.917s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	15.434s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	15.434s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	15.434s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.685m	5.638ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.983s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.700s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.941s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.634s		0	1	0.00
		chip_sw_lc_ctrl_transition	15.434s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.850m	8.714ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.867m	11.850ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	12.360s		0	1	0.00
		chip_prim_tl_access	4.517m	8.912ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.369s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.009s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.935s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.583s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.190s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.777s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.483s		0	1	0.00
		chip_rv_dm_lc_disabled	21.499m	31.881ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.277m	4.320ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	36.210s	10.360us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.660m	5.802ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.770m	4.885ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.006m	4.429ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	44.550s	10.180us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.049m	4.468ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.417m	4.202ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.792m	4.625ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	38.570s	10.160us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.850m	8.714ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	15.434s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	32.930s	10.400us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.540m	5.969ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.451m	4.511ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.278s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.278s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.679s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.984m	5.267ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	15.767s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.850m	8.714ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	43.480s	10.220us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	14.754s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.269s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.166m	5.678ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.166m	5.678ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.166m	5.678ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.057m	4.778ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.867m	11.850ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.867m	11.850ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.824m	9.857ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.858s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.360s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	20.084m	14.540ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.270m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	15.434s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.057m	4.778ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.850m	8.714ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.824m	9.857ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.447m	4.219ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.057m	4.778ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.850m	8.714ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.824m	9.857ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.447m	4.219ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	15.434s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.174s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	17.917s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.983s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.700s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.941s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.634s		0	1	0.00
		chip_sw_lc_ctrl_transition	15.434s		0	1	0.00
		chip_prim_tl_access	4.517m	8.912ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.517m	8.912ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	25.684s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	20.368s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	14.521s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.269s		0	1	0.00
		chip_sw_aes_enc_jitter_en	36.210s	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	44.550s	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	43.480s	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	38.570s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.858s		0	1	0.00
		chip_sw_clkmgr_jitter	4.188m	4.660ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.399m	5.843ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.399m	5.843ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.558m	3.761ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.387m	4.628ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.401m	4.871ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	9.556m	7.077ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.282m	5.057ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.575m	4.462ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.447m	4.219ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	24.913m	20.019ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	24.913m	20.019ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.569m	4.127ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.379m	3.472ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.410m	4.170ms	1	1	100.00
		chip_sw_csrng_smoketest	3.929m	4.493ms	1	1	100.00
		chip_sw_gpio_smoketest	3.914m	4.889ms	1	1	100.00
		chip_sw_hmac_smoketest	4.653m	5.438ms	1	1	100.00
		chip_sw_kmac_smoketest	3.663m	3.852ms	1	1	100.00
		chip_sw_otbn_smoketest	4.672m	4.157ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.900m	4.409ms	1	1	100.00
		chip_sw_rv_plic_smoketest	4.011m	3.695ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.694m	5.557ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.569m	3.597ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.773m	4.554ms	1	1	100.00
		chip_sw_uart_smoketest	3.856m	4.659ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.183s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	13.623s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.968m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	14.018s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.457m	4.614ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.838m	5.973ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.271m	4.853ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.989m	5.804ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.058s		0	1	0.00
		chip_rv_dm_lc_disabled	21.499m	31.881ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	14.115s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.194s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	11.644s		0	1	0.00
		chip_sw_lc_walkthrough_rma	13.803s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	18.058s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	19.600s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.677s		0	1	0.00
		rom_volatile_raw_unlock	12.174s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	12.442s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.845m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.858m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.627m	4.920ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.627m	4.920ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.200s		0	1	0.00
		chip_same_csr_outstanding	8.690s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.200s		0	1	0.00
		chip_same_csr_outstanding	8.690s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	2.568m	420.095us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.420s	13.646us	1	1	100.00
		xbar_smoke_large_delays	4.384m	2.295ms	1	1	100.00
		xbar_smoke_slow_rsp	6.168m	2.244ms	1	1	100.00
		xbar_random_zero_delays	1.013m	50.265us	1	1	100.00
		xbar_random_large_delays	9.440m	4.702ms	1	1	100.00
		xbar_random_slow_rsp	15.587m	5.393ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	2.143m	252.132us	1	1	100.00
		xbar_error_and_unmapped_addr	21.040s	18.474us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.912m	507.730us	1	1	100.00
		xbar_error_and_unmapped_addr	21.040s	18.474us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	13.120s	21.013us	1	1	100.00
		xbar_access_same_device_slow_rsp	44.068m	17.144ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.134m	64.124us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	9.362m	1.303ms	1	1	100.00
		xbar_stress_all_with_error	8.995m	1.560ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	11.607m	271.764us	1	1	100.00
		xbar_stress_all_with_reset_error	38.980s	53.776us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.644s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.527s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.219s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.670s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.277s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	13.816s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.775s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.570s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	13.134s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.708s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.649s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.725s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.631s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.558s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.792s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.835s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.011s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.067s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.416s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.057s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.879s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.389s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	13.151s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.023s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	11.646s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	11.113s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.503s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.305s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.098s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.201s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.388s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.998s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.943s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.645s		0	1	0.00
		rom_e2e_asm_init_dev	11.274s		0	1	0.00
		rom_e2e_asm_init_prod	11.562s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.435s		0	1	0.00
		rom_e2e_asm_init_rma	12.287s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.838s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.786s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.220s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.143s		0	1	0.00
V2		TOTAL			67	205	32.68
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.503m	4.648ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.046m	3.559ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.690s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.623s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.902s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.269s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	20.084m	14.540ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	16.858s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	20.131m	14.341ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.997s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.693s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.690s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.623s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.902s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.572s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.630s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.650s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.973s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.604m	15.502ms	1	1	100.00
		chip_sw_entropy_src_kat_test	3.942m	4.965ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	4.287m	5.353ms	1	1	100.00
		chip_plic_all_irqs_0	9.119m	5.718ms	1	1	100.00
		chip_plic_all_irqs_10	10.837m	6.293ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.385m	4.808ms	1	1	100.00
		chip_sw_dma_abort	4.991m	4.764ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.674s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.726s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.381s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.740s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	13.445s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.657s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	12.907s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.880s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.934s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	12.443s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.281m	3.794ms	1	1	100.00
		chip_sw_mbx_smoketest	3.960m	5.211ms	1	1	100.00
		TOTAL			81	250	32.40

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.81389533031231220688459183603634146474334873259703790228385464843465978243397
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 128.742s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.51811147701870959546404937798074154032158356041462179578278298118492966999839
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 124.700s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.85890452974786664027179594840574294909866752681756636536962816386807470611485
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 129.733s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.73145575860511420847849204934770285447467072920581461111678707988505326029899
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 119.181s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.82162849599934575247934259694250872818054322535302637514390694962206476906295
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 109.391s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.87858808924154733410803819269890104999102615354116014240308394711661707350572
    Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.84738297128269240857995133625220490841327605219749833253372939435446178659626
    Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.93544689333933588782237186036454630244935726588752902610694214999734676173799
    Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.35515799147666502648726290490715227350125938423072723520781310209322608910770
    Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.2442002365733469622391895697508954846483727284378411814064361504060590678243
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.61034850694690880692582094076742541835776141802286613465342226605556469725661
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.1661785802437321721345527806658848447757821306869114280832884490266671162163
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.76558115523701576950840590987249475194427640690366784187380403446271227119892
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.105226867600898830215167145013139174257300312139732112552372691895840079214198
Line 436, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.712234 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.712234 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.95795244685647662730633789454864695814929563284214501414297164581490251416635
Line 409, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.491353 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.491353 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.70687250409053904081650384520747310606539543785284285020555238193973991506078
Line 414, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18026.885464 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.885464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.57766862513057100171511144628483618783865255100094402510227229856117689462008
Line 441, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8714.030600 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (114220972610384427195563851315417658077552578027846998297784357995282594224833 [0xfc86c78d707ad2433b6440e2edbaf08052f87695fd255030b830f681122b5ac1] vs 43514182647489614141471741717251752089119744314420196796372580703172205476180 [0x603427932e9a65340002db7a7a7ccbec3323b33b26b98f2c902c35f3360ff954])
  UVM_INFO @ 8714.030600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.13336426991897095803706547460579922624489793787842076188270825328469470360942
Line 452, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 5638.353576 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (114240906310373859408098614225566892056426465635495619961605129049168254091698 [0xfc920fc377272ff9f45b2826103e9e5672c955d675c09d2f17385a13d94c41b2] vs 66548614724778080445932910941837674539583506968427900811911940388089223991585 [0x93212e5e91992d463199c9eefad298db584f20d03da86d2f6cd1469c06f05121])
  UVM_INFO @ 5638.353576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:
- Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_hmac_trans.79728075679365863489885580670456292190629573245167073030875592812885108875424
    Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
```
  UVM_ERROR @ 12018.600427 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.600427 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_otbn_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_otbn_trans.29991721079475243981676657592557034181894800688724109045574955641975019607978
    Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log
```
  UVM_ERROR @ 12018.441001 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.441001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47274) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.79702777867648050696973873936209958718022287451835362377191716112335607381552
Line 6260, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3736.829568 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47274) { a_addr: 'h30480000  a_data: 'h53bc68c3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h0  a_user: 'h2694f  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3736.829568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.93697902491608692906650868086397451592480960510599752467793813905607379670412
Line 6260, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3358.443891 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47274) { a_addr: 'h30480000  a_data: 'hdcd1723d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h0  a_user: 'h2690e  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3358.443891 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.91811515755704190469656067443156399024227598126635124165983018837314113514181
    Line 597, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.9704191046672492774000164291370299056342058734816889092866856522975019839126
    Line 463, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3999.155535 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3999.155535 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.114998590104660964286103340937177008114080817292201637353870966522766667064418
    Line 692, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 9085.657330 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 9085.657330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.8921018204025881444466974523117269267269944533496406928689677927406949689759
    Line 417, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3761.214729 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3761.214729 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.37316970295286193258946168648030634209509480328513467222821146607128693251592
    Line 419, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4627.653122 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4627.653122 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.20168041355792262386227125564335600030557412239214644810386084875989222661641
    Line 409, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4080.879093 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4080.879093 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.64523589448900243920511245625355494033927043501394958830305846576588962583297
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 7077.176364 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 7077.176364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.89751658035238681841581210283155575378098685250871279161420591545803263952416
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.113006798847667493541846863760123345201160446451909596150499020465209579726284
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4920.440352 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4920.440352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.66809969683453619271933488942708948819467055240505233583006999690973650367000
    Line 372, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13676.674232 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13676.674232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.22168714756644747912471150107956961578837729047843522661090894522263256711439
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.108003518739355375275926101362579348471217384886442963809948769020385778959078
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4763.540748 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4763.540748 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```