AES/MASKED Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	188.735us	1	1	100.00
V1	smoke	aes_smoke	4.000s	124.080us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	146.139us	1	1	100.00
V1	csr_rw	aes_csr_rw	3.000s	56.614us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	1.903ms	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	538.915us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	67.037us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	56.614us	1	1	100.00
		aes_csr_aliasing	4.000s	538.915us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	4.000s	124.080us	1	1	100.00
		aes_config_error	4.000s	280.716us	1	1	100.00
		aes_stress	7.000s	144.495us	1	1	100.00
V2	key_length	aes_smoke	4.000s	124.080us	1	1	100.00
		aes_config_error	4.000s	280.716us	1	1	100.00
		aes_stress	7.000s	144.495us	1	1	100.00
V2	back2back	aes_stress	7.000s	144.495us	1	1	100.00
		aes_b2b	10.000s	766.736us	1	1	100.00
V2	backpressure	aes_stress	7.000s	144.495us	1	1	100.00
V2	multi_message	aes_smoke	4.000s	124.080us	1	1	100.00
		aes_config_error	4.000s	280.716us	1	1	100.00
		aes_stress	7.000s	144.495us	1	1	100.00
		aes_alert_reset	7.000s	576.062us	1	1	100.00
V2	failure_test	aes_man_cfg_err	3.000s	108.565us	1	1	100.00
		aes_config_error	4.000s	280.716us	1	1	100.00
		aes_alert_reset	7.000s	576.062us	1	1	100.00
V2	trigger_clear_test	aes_clear	6.000s	154.877us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	606.520us	1	1	100.00
V2	reset_recovery	aes_alert_reset	7.000s	576.062us	1	1	100.00
V2	stress	aes_stress	7.000s	144.495us	1	1	100.00
V2	sideload	aes_stress	7.000s	144.495us	1	1	100.00
		aes_sideload	5.000s	92.150us	1	1	100.00
V2	deinitialization	aes_deinit	5.000s	1.477ms	1	1	100.00
V2	stress_all	aes_stress_all	5.000s	426.334us	1	1	100.00
V2	alert_test	aes_alert_test	3.000s	74.226us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	134.421us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	134.421us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	146.139us	1	1	100.00
		aes_csr_rw	3.000s	56.614us	1	1	100.00
		aes_csr_aliasing	4.000s	538.915us	1	1	100.00
		aes_same_csr_outstanding	4.000s	177.748us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	146.139us	1	1	100.00
		aes_csr_rw	3.000s	56.614us	1	1	100.00
		aes_csr_aliasing	4.000s	538.915us	1	1	100.00
		aes_same_csr_outstanding	4.000s	177.748us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	6.000s	320.797us	1	1	100.00
V2S	fault_inject	aes_fi	5.000s	85.121us	1	1	100.00
		aes_control_fi	4.000s	148.081us	1	1	100.00
		aes_cipher_fi	41.000s	10.003ms	0	1	0.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	103.109us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	103.109us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	103.109us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	103.109us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	1.129ms	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	893.574us	1	1	100.00
		aes_tl_intg_err	4.000s	327.030us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	327.030us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	7.000s	576.062us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	103.109us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	124.080us	1	1	100.00
		aes_stress	7.000s	144.495us	1	1	100.00
		aes_alert_reset	7.000s	576.062us	1	1	100.00
		aes_core_fi	3.000s	67.770us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	103.109us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	121.905us	1	1	100.00
		aes_stress	7.000s	144.495us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	144.495us	1	1	100.00
		aes_sideload	5.000s	92.150us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	121.905us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	121.905us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	121.905us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	121.905us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	121.905us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	144.495us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	144.495us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	85.121us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	85.121us	1	1	100.00
		aes_control_fi	4.000s	148.081us	1	1	100.00
		aes_cipher_fi	41.000s	10.003ms	0	1	0.00
		aes_ctr_fi	4.000s	50.568us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	85.121us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	85.121us	1	1	100.00
		aes_control_fi	4.000s	148.081us	1	1	100.00
		aes_cipher_fi	41.000s	10.003ms	0	1	0.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	41.000s	10.003ms	0	1	0.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	85.121us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	85.121us	1	1	100.00
		aes_control_fi	4.000s	148.081us	1	1	100.00
		aes_ctr_fi	4.000s	50.568us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	85.121us	1	1	100.00
		aes_control_fi	4.000s	148.081us	1	1	100.00
		aes_cipher_fi	41.000s	10.003ms	0	1	0.00
		aes_ctr_fi	4.000s	50.568us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	7.000s	576.062us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	85.121us	1	1	100.00
		aes_control_fi	4.000s	148.081us	1	1	100.00
		aes_cipher_fi	41.000s	10.003ms	0	1	0.00
		aes_ctr_fi	4.000s	50.568us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	85.121us	1	1	100.00
		aes_control_fi	4.000s	148.081us	1	1	100.00
		aes_cipher_fi	41.000s	10.003ms	0	1	0.00
		aes_ctr_fi	4.000s	50.568us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	85.121us	1	1	100.00
		aes_control_fi	4.000s	148.081us	1	1	100.00
		aes_ctr_fi	4.000s	50.568us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	85.121us	1	1	100.00
		aes_control_fi	4.000s	148.081us	1	1	100.00
		aes_cipher_fi	41.000s	10.003ms	0	1	0.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	25.000s	1.712ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 1 failures:

  • Test aes_cipher_fi has 1 failures.

    • 0.aes_cipher_fi.9803953434064231460634748285231361559743440483638401273739095273515154462616
      Line 147, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_cipher_fi/latest/run.log

        UVM_FATAL @ 10003246306 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10003246306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.10775413876322990331460621194597689450640341118371331433221395155813448980165
      Line 847, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1711553514 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 1711553514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---