DMA Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	6.000s	607.170us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	5.000s	295.265us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	597.666us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	32.904us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	29.166us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	12.000s	1.010ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	158.254us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	3.000s	29.342us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	29.166us	1	1	100.00
		dma_csr_aliasing	7.000s	158.254us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	39.000s	2.038ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	8.050m	184.793ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	1.433m	6.646ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	1.433m	6.646ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	8.050m	184.793ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	8.200m	141.631ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	1.433m	6.646ms	1	1	100.00
V2	dma_abort	dma_abort	8.000s	806.725us	1	1	100.00
V2	dma_stress_all	dma_stress_all	34.000s	2.702ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	13.707us	1	1	100.00
V2	intr_test	dma_intr_test	3.000s	50.567us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	47.390us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	47.390us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	32.904us	1	1	100.00
		dma_csr_rw	2.000s	29.166us	1	1	100.00
		dma_csr_aliasing	7.000s	158.254us	1	1	100.00
		dma_same_csr_outstanding	4.000s	402.658us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	32.904us	1	1	100.00
		dma_csr_rw	2.000s	29.166us	1	1	100.00
		dma_csr_aliasing	7.000s	158.254us	1	1	100.00
		dma_same_csr_outstanding	4.000s	402.658us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	27.000s	1.046ms	1	1	100.00
		dma_generic_stress	8.200m	141.631ms	1	1	100.00
		dma_handshake_stress	1.433m	6.646ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	9.000s	1.172ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	1.112ms	1	1	100.00
		dma_sec_cm	3.000s	56.705us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.183m	3.600ms	1	1	100.00
		dma_longer_transfer	5.000s	190.148us	1	1	100.00
		dma_stress_all_with_rand_reset	4.000s	436.363us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:946) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.94953172755726172387389707657000500807016527524171079809641169590487067503743
      Line 90, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  436363061ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  436363061ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---