EDN Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.840s	51.733us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.700s	41.017us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.830s	39.452us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.160s	188.191us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	0.860s	59.625us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.840s	16.552us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.830s	39.452us	1	1	100.00
		edn_csr_aliasing	0.860s	59.625us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	6.590s	1.162ms	1	1	100.00
V2	csrng_commands	edn_genbits	6.590s	1.162ms	1	1	100.00
V2	genbits	edn_genbits	6.590s	1.162ms	1	1	100.00
V2	interrupts	edn_intr	0.850s	22.752us	1	1	100.00
V2	alerts	edn_alert	0.980s	49.230us	1	1	100.00
V2	errs	edn_err	1.110s	33.183us	1	1	100.00
V2	disable	edn_disable	0.750s	21.387us	1	1	100.00
		edn_disable_auto_req_mode	0.920s	75.815us	1	1	100.00
V2	stress_all	edn_stress_all	1.280s	230.901us	1	1	100.00
V2	intr_test	edn_intr_test	0.740s	54.901us	1	1	100.00
V2	alert_test	edn_alert_test	0.810s	34.751us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.200s	44.385us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.200s	44.385us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.700s	41.017us	1	1	100.00
		edn_csr_rw	0.830s	39.452us	1	1	100.00
		edn_csr_aliasing	0.860s	59.625us	1	1	100.00
		edn_same_csr_outstanding	1.300s	35.429us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.700s	41.017us	1	1	100.00
		edn_csr_rw	0.830s	39.452us	1	1	100.00
		edn_csr_aliasing	0.860s	59.625us	1	1	100.00
		edn_same_csr_outstanding	1.300s	35.429us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.790s	280.067us	1	1	100.00
		edn_tl_intg_err	1.590s	199.715us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.860s	16.039us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.980s	49.230us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.790s	280.067us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.790s	280.067us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.790s	280.067us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.790s	280.067us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.980s	49.230us	1	1	100.00
		edn_sec_cm	3.790s	280.067us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.980s	49.230us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.590s	199.715us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	54.690s	3.787ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00