ENTROPY_SRC/RNG_16BITS Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 22.932us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 445.683us 1 1 100.00
V1 csr_rw entropy_src_csr_rw 2.000s 194.715us 1 1 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 9.000s 382.223us 1 1 100.00
V1 csr_aliasing entropy_src_csr_aliasing 4.000s 46.477us 1 1 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 3.000s 113.790us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 2.000s 194.715us 1 1 100.00
entropy_src_csr_aliasing 4.000s 46.477us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware entropy_src_smoke 4.000s 22.932us 1 1 100.00
entropy_src_rng 3.533m 18.118ms 1 1 100.00
entropy_src_fw_ov 1.750m 12.211ms 1 1 100.00
V2 firmware_mode entropy_src_fw_ov 1.750m 12.211ms 1 1 100.00
V2 rng_mode entropy_src_rng 3.533m 18.118ms 1 1 100.00
V2 rng_max_rate entropy_src_rng_max_rate 1.200m 8.077ms 1 1 100.00
V2 health_checks entropy_src_rng 3.533m 18.118ms 1 1 100.00
V2 conditioning entropy_src_rng 3.533m 18.118ms 1 1 100.00
V2 interrupts entropy_src_rng 3.533m 18.118ms 1 1 100.00
entropy_src_intr 56.000s 10.143ms 0 1 0.00
V2 alerts entropy_src_rng 3.533m 18.118ms 1 1 100.00
entropy_src_functional_alerts 6.000s 184.398us 1 1 100.00
V2 stress_all entropy_src_stress_all 4.067m 10.399ms 1 1 100.00
V2 functional_errors entropy_src_functional_errors 3.000s 109.824us 1 1 100.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 23.000s 1.401ms 1 1 100.00
V2 intr_test entropy_src_intr_test 3.000s 47.716us 1 1 100.00
V2 alert_test entropy_src_alert_test 3.000s 41.771us 1 1 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 4.000s 29.257us 1 1 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 4.000s 29.257us 1 1 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 445.683us 1 1 100.00
entropy_src_csr_rw 2.000s 194.715us 1 1 100.00
entropy_src_csr_aliasing 4.000s 46.477us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 580.543us 1 1 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 445.683us 1 1 100.00
entropy_src_csr_rw 2.000s 194.715us 1 1 100.00
entropy_src_csr_aliasing 4.000s 46.477us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 580.543us 1 1 100.00
V2 TOTAL 11 12 91.67
V2S tl_intg_err entropy_src_sec_cm 4.000s 207.930us 1 1 100.00
entropy_src_tl_intg_err 7.000s 2.273ms 1 1 100.00
V2S sec_cm_config_regwen entropy_src_rng 3.533m 18.118ms 1 1 100.00
entropy_src_cfg_regwen 3.000s 21.094us 1 1 100.00
V2S sec_cm_config_mubi entropy_src_rng 3.533m 18.118ms 1 1 100.00
V2S sec_cm_config_redun entropy_src_rng 3.533m 18.118ms 1 1 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 3.533m 18.118ms 1 1 100.00
entropy_src_fw_ov 1.750m 12.211ms 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 3.000s 109.824us 1 1 100.00
entropy_src_sec_cm 4.000s 207.930us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 3.000s 109.824us 1 1 100.00
entropy_src_sec_cm 4.000s 207.930us 1 1 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 3.533m 18.118ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 3.000s 109.824us 1 1 100.00
entropy_src_sec_cm 4.000s 207.930us 1 1 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 3.000s 109.824us 1 1 100.00
entropy_src_sec_cm 4.000s 207.930us 1 1 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 3.000s 109.824us 1 1 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 6.000s 184.398us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 2.273ms 1 1 100.00
V2S TOTAL 3 3 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 1.633m 15.111ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 21 22 95.45

Failure Buckets