HMAC Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 1.730s 103.850us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.830s 204.222us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.760s 443.107us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 3.550s 112.875us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.350s 161.330us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.520s 138.108us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.760s 443.107us 1 1 100.00
hmac_csr_aliasing 5.350s 161.330us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 15.710s 419.795us 1 1 100.00
V2 back_pressure hmac_back_pressure 52.060s 2.659ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.480s 173.267us 1 1 100.00
hmac_test_sha384_vectors 18.340s 244.157us 1 1 100.00
hmac_test_sha512_vectors 6.897m 13.114ms 1 1 100.00
hmac_test_hmac256_vectors 7.680s 271.313us 1 1 100.00
hmac_test_hmac384_vectors 6.790s 1.333ms 1 1 100.00
hmac_test_hmac512_vectors 9.180s 1.210ms 1 1 100.00
V2 burst_wr hmac_burst_wr 11.990s 971.183us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.209m 1.425ms 1 1 100.00
V2 error hmac_error 46.380s 16.543ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.420m 2.748ms 1 1 100.00
V2 save_and_restore hmac_smoke 1.730s 103.850us 1 1 100.00
hmac_long_msg 15.710s 419.795us 1 1 100.00
hmac_back_pressure 52.060s 2.659ms 1 1 100.00
hmac_datapath_stress 1.209m 1.425ms 1 1 100.00
hmac_burst_wr 11.990s 971.183us 1 1 100.00
hmac_stress_all 9.092m 91.714ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 1.730s 103.850us 1 1 100.00
hmac_long_msg 15.710s 419.795us 1 1 100.00
hmac_back_pressure 52.060s 2.659ms 1 1 100.00
hmac_datapath_stress 1.209m 1.425ms 1 1 100.00
hmac_wipe_secret 1.420m 2.748ms 1 1 100.00
hmac_test_sha256_vectors 7.480s 173.267us 1 1 100.00
hmac_test_sha384_vectors 18.340s 244.157us 1 1 100.00
hmac_test_sha512_vectors 6.897m 13.114ms 1 1 100.00
hmac_test_hmac256_vectors 7.680s 271.313us 1 1 100.00
hmac_test_hmac384_vectors 6.790s 1.333ms 1 1 100.00
hmac_test_hmac512_vectors 9.180s 1.210ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 1.730s 103.850us 1 1 100.00
hmac_long_msg 15.710s 419.795us 1 1 100.00
hmac_back_pressure 52.060s 2.659ms 1 1 100.00
hmac_datapath_stress 1.209m 1.425ms 1 1 100.00
hmac_burst_wr 11.990s 971.183us 1 1 100.00
hmac_error 46.380s 16.543ms 1 1 100.00
hmac_wipe_secret 1.420m 2.748ms 1 1 100.00
hmac_test_sha256_vectors 7.480s 173.267us 1 1 100.00
hmac_test_sha384_vectors 18.340s 244.157us 1 1 100.00
hmac_test_sha512_vectors 6.897m 13.114ms 1 1 100.00
hmac_test_hmac256_vectors 7.680s 271.313us 1 1 100.00
hmac_test_hmac384_vectors 6.790s 1.333ms 1 1 100.00
hmac_test_hmac512_vectors 9.180s 1.210ms 1 1 100.00
hmac_stress_all 9.092m 91.714ms 1 1 100.00
V2 stress_all hmac_stress_all 9.092m 91.714ms 1 1 100.00
V2 alert_test hmac_alert_test 0.570s 13.710us 1 1 100.00
V2 intr_test hmac_intr_test 0.560s 200.067us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.330s 61.988us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.330s 61.988us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.830s 204.222us 1 1 100.00
hmac_csr_rw 0.760s 443.107us 1 1 100.00
hmac_csr_aliasing 5.350s 161.330us 1 1 100.00
hmac_same_csr_outstanding 1.690s 44.358us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.830s 204.222us 1 1 100.00
hmac_csr_rw 0.760s 443.107us 1 1 100.00
hmac_csr_aliasing 5.350s 161.330us 1 1 100.00
hmac_same_csr_outstanding 1.690s 44.358us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.800s 63.724us 1 1 100.00
hmac_tl_intg_err 1.410s 167.869us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.410s 167.869us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 1.730s 103.850us 1 1 100.00
V3 stress_reset hmac_stress_reset 5.800s 295.619us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 3.287m 82.587ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.580s 34.815us 1 1 100.00
TOTAL 28 28 100.00