I2C Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	49.390s	1.529ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.890s	430.817us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.750s	66.469us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.680s	24.741us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.530s	1.445ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.200s	53.912us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.400s	110.572us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.680s	24.741us	1	1	100.00
		i2c_csr_aliasing	1.200s	53.912us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.830s	5.941us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	1.030s	26.868us	0	1	0.00
V2	host_maxperf	i2c_host_perf	44.240s	5.246ms	1	1	100.00
V2	host_override	i2c_host_override	0.730s	35.314us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.314m	17.936ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	23.750s	5.391ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.230s	107.671us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.960s	1.360ms	1	1	100.00
		i2c_host_fifo_reset_rx	2.610s	175.445us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	59.900s	2.714ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.850s	757.616us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.630s	104.864us	0	1	0.00
V2	target_glitch	i2c_target_glitch	3.250s	3.334ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	59.920s	49.363ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	2.060s	432.314us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	9.940s	276.747us	1	1	100.00
		i2c_target_intr_smoke	4.820s	621.855us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.030s	179.090us	1	1	100.00
		i2c_target_fifo_reset_tx	1.230s	2.424ms	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	11.357m	52.783ms	1	1	100.00
		i2c_target_stress_rd	9.940s	276.747us	1	1	100.00
		i2c_target_intr_stress_wr	3.710s	4.132ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.920s	1.386ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.910s	3.397ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.400s	2.339ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.720s	1.509ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.100s	95.324us	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.840s	220.256us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	44.240s	5.246ms	1	1	100.00
		i2c_host_perf_precise	1.140s	83.480us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.850s	757.616us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.620s	273.089us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.290s	1.888ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.910s	580.683us	1	1	100.00
		i2c_target_nack_txstretch	1.400s	169.660us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.620s	338.226us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.190s	1.146ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.590s	15.795us	1	1	100.00
V2	intr_test	i2c_intr_test	0.730s	68.699us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.000s	130.228us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.000s	130.228us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.750s	66.469us	1	1	100.00
		i2c_csr_rw	0.680s	24.741us	1	1	100.00
		i2c_csr_aliasing	1.200s	53.912us	1	1	100.00
		i2c_same_csr_outstanding	0.860s	22.945us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.750s	66.469us	1	1	100.00
		i2c_csr_rw	0.680s	24.741us	1	1	100.00
		i2c_csr_aliasing	1.200s	53.912us	1	1	100.00
		i2c_same_csr_outstanding	0.860s	22.945us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.660s	71.564us	1	1	100.00
		i2c_sec_cm	0.880s	71.478us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.660s	71.564us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	11.930s	1.023ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.080s	287.028us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	1.130s	104.188us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.74241595910749855443044808420269327417239501832292040812753845525774409691272
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @   5941232 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @   5941232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.83631911296552330154689488720958636121020559500023254932598748886391606990014
      Line 95, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @  26867524 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  26867524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.43703757744847655274985417089995570783208613746298795543212639238707047072935
      Line 101, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 104187502 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 104187502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.56681134484309720361677338057574511958713037124496579469784453869468095895039
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 3334358637 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 3334358637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.47083392560856546732010519086638913680437990591926712610317455569355045996058
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

            Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
        UVM_ERROR @ 287027994 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
        UVM_INFO @ 287027994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.18732857816424062942243295190511270727843927345468828962352542866641797262321
      Line 103, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1022961863 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1022961863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.114826098325202766298268122339454470230358042101751086295472162505889997458350
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_FATAL @ 104864367 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xbe126f94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 104864367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---