KEYMGR Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 2.070s 156.989us 1 1 100.00
V1 random keymgr_random 4.500s 135.759us 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.010s 144.453us 1 1 100.00
V1 csr_rw keymgr_csr_rw 1.070s 122.735us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 9.900s 261.389us 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 4.220s 875.901us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.740s 32.537us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.070s 122.735us 1 1 100.00
keymgr_csr_aliasing 4.220s 875.901us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 3.070s 123.609us 1 1 100.00
V2 sideload keymgr_sideload 3.120s 1.050ms 1 1 100.00
keymgr_sideload_kmac 2.300s 296.944us 1 1 100.00
keymgr_sideload_aes 2.000s 54.712us 1 1 100.00
keymgr_sideload_otbn 2.390s 294.400us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 12.140s 1.120ms 1 1 100.00
V2 lc_disable keymgr_lc_disable 1.960s 46.657us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.990s 35.561us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 3.650s 1.544ms 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 3.430s 122.346us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 1.780s 73.938us 1 1 100.00
V2 stress_all keymgr_stress_all 11.990s 1.851ms 1 1 100.00
V2 intr_test keymgr_intr_test 0.920s 20.146us 1 1 100.00
V2 alert_test keymgr_alert_test 0.860s 14.813us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 1.630s 92.664us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 1.630s 92.664us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.010s 144.453us 1 1 100.00
keymgr_csr_rw 1.070s 122.735us 1 1 100.00
keymgr_csr_aliasing 4.220s 875.901us 1 1 100.00
keymgr_same_csr_outstanding 3.320s 448.353us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.010s 144.453us 1 1 100.00
keymgr_csr_rw 1.070s 122.735us 1 1 100.00
keymgr_csr_aliasing 4.220s 875.901us 1 1 100.00
keymgr_same_csr_outstanding 3.320s 448.353us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 12.980s 632.071us 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 12.980s 632.071us 1 1 100.00
keymgr_tl_intg_err 2.970s 240.140us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 2.520s 508.709us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 2.520s 508.709us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 2.520s 508.709us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 2.520s 508.709us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 14.590s 1.239ms 1 1 100.00
V2S prim_count_check keymgr_sec_cm 12.980s 632.071us 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 12.980s 632.071us 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 2.970s 240.140us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 2.520s 508.709us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 3.070s 123.609us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 4.500s 135.759us 1 1 100.00
keymgr_csr_rw 1.070s 122.735us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 4.500s 135.759us 1 1 100.00
keymgr_csr_rw 1.070s 122.735us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 4.500s 135.759us 1 1 100.00
keymgr_csr_rw 1.070s 122.735us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 1.960s 46.657us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 3.430s 122.346us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 3.430s 122.346us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 4.500s 135.759us 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 1.790s 74.473us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 12.980s 632.071us 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 12.980s 632.071us 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 12.980s 632.071us 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 2.470s 74.192us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 1.960s 46.657us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 12.980s 632.071us 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 12.980s 632.071us 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 12.980s 632.071us 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 2.470s 74.192us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 2.470s 74.192us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 12.980s 632.071us 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 2.470s 74.192us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 12.980s 632.071us 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 2.470s 74.192us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 6.720s 527.414us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00