| V1 |
smoke |
keymgr_dpe_smoke |
29.420s |
16.745ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
0.940s |
118.618us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
0.960s |
83.021us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
3.220s |
97.650us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
5.740s |
220.645us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.090s |
156.310us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
0.960s |
83.021us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.740s |
220.645us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
0.700s |
48.745us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.030s |
83.106us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
1.920s |
175.563us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
1.920s |
175.563us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
0.940s |
118.618us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.960s |
83.021us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.740s |
220.645us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.060s |
25.364us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
0.940s |
118.618us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.960s |
83.021us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.740s |
220.645us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.060s |
25.364us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
5.380s |
267.264us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
1.680s |
56.278us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
1.070s |
73.787us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
1.070s |
73.787us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
1.070s |
73.787us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
1.070s |
73.787us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
1.900s |
73.870us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
5.380s |
267.264us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
5.380s |
267.264us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |