| V1 |
smoke |
kmac_smoke |
1.188m |
11.540ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
0.910s |
48.971us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
0.920s |
68.203us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
7.680s |
746.441us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
7.160s |
2.159ms |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
1.280s |
50.028us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
0.920s |
68.203us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.160s |
2.159ms |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.690s |
14.263us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.910s |
142.724us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
39.565m |
103.454ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
10.299m |
78.188ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
33.920s |
4.332ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
28.180s |
2.455ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
18.520s |
3.481ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
18.047m |
784.120ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
28.321m |
22.590ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
28.692m |
60.329ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.640s |
449.544us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.520s |
536.858us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
3.230m |
10.340ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
4.970m |
16.917ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
1.812m |
16.614ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
33.980s |
4.671ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
3.703m |
16.432ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
6.900s |
734.685us |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
6.680s |
214.145us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
1.020s |
40.883us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
1.340s |
41.513us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
2.920s |
259.045us |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.480s |
111.291us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
19.607m |
227.934ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.810s |
20.203us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
1.120s |
21.030us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
2.420s |
227.680us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
2.420s |
227.680us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
0.910s |
48.971us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
0.920s |
68.203us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.160s |
2.159ms |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.790s |
154.485us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
0.910s |
48.971us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
0.920s |
68.203us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.160s |
2.159ms |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.790s |
154.485us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.670s |
117.896us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.670s |
117.896us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.670s |
117.896us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.670s |
117.896us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
3.920s |
309.101us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
1.153m |
13.952ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
2.280s |
585.834us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
2.280s |
585.834us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.480s |
111.291us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
1.188m |
11.540ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
3.230m |
10.340ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.670s |
117.896us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
1.153m |
13.952ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
1.153m |
13.952ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
1.153m |
13.952ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
1.188m |
11.540ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.480s |
111.291us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
1.153m |
13.952ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
1.796m |
22.932ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
1.188m |
11.540ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
3.731m |
6.364ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |