KMAC/UNMASKED Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	11.150s	703.636us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.130s	56.140us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.120s	37.474us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.190s	3.784ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.200s	2.183ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.740s	146.482us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.120s	37.474us	1	1	100.00
		kmac_csr_aliasing	7.200s	2.183ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.710s	13.557us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.200s	65.319us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	14.826m	363.626ms	1	1	100.00
V2	burst_write	kmac_burst_write	8.152m	36.562ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.847m	168.427ms	1	1	100.00
		kmac_test_vectors_sha3_256	35.360s	9.869ms	1	1	100.00
		kmac_test_vectors_sha3_384	17.716m	177.042ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.400s	265.708us	1	1	100.00
		kmac_test_vectors_shake_128	2.018m	3.586ms	1	1	100.00
		kmac_test_vectors_shake_256	1.625m	30.476ms	1	1	100.00
		kmac_test_vectors_kmac	1.930s	40.274us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.540s	72.434us	1	1	100.00
V2	sideload	kmac_sideload	4.399m	12.269ms	1	1	100.00
V2	app	kmac_app	3.247m	5.526ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.066m	14.625ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	9.730s	635.422us	1	1	100.00
V2	error	kmac_error	5.281m	65.863ms	1	1	100.00
V2	key_error	kmac_key_error	3.410s	2.324ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	7.720s	10.266ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	14.410s	10.861ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	8.620s	158.445us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	6.950s	2.390ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.380s	266.602us	1	1	100.00
V2	stress_all	kmac_stress_all	27.108m	296.048ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.680s	41.249us	1	1	100.00
V2	alert_test	kmac_alert_test	0.760s	27.075us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.710s	39.018us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.710s	39.018us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.130s	56.140us	1	1	100.00
		kmac_csr_rw	1.120s	37.474us	1	1	100.00
		kmac_csr_aliasing	7.200s	2.183ms	1	1	100.00
		kmac_same_csr_outstanding	1.070s	88.159us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.130s	56.140us	1	1	100.00
		kmac_csr_rw	1.120s	37.474us	1	1	100.00
		kmac_csr_aliasing	7.200s	2.183ms	1	1	100.00
		kmac_same_csr_outstanding	1.070s	88.159us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.150s	178.375us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.150s	178.375us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.150s	178.375us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.150s	178.375us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.670s	1.001ms	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	40.210s	5.029ms	1	1	100.00
		kmac_tl_intg_err	3.280s	386.735us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.280s	386.735us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.380s	266.602us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	11.150s	703.636us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.399m	12.269ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.150s	178.375us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	40.210s	5.029ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	40.210s	5.029ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	40.210s	5.029ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	11.150s	703.636us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.380s	266.602us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	40.210s	5.029ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.860s	691.348us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	11.150s	703.636us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.188m	2.864ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.43535953896157234103624389816259782834961143004407551106411777215720035658861
      Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10265997912 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5e8f8000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 10265997912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---