MBX Simulation Results

Monday September 08 2025 16:06:54 UTC

GitHub Revision: 83a1436

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	1.900m	23.310ms	1	1	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	2.000s	21.842us	1	1	100.00
V1	csr_rw	mbx_csr_rw	2.000s	79.942us	1	1	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	4.000s	48.922us	1	1	100.00
V1	csr_aliasing	mbx_csr_aliasing	3.000s	40.435us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	2.000s	136.502us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	2.000s	79.942us	1	1	100.00
		mbx_csr_aliasing	3.000s	40.435us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	mbx_stress	mbx_stress	7.000s	148.649us	0	1	0.00
V2	mbx_max_activity	mbx_stress_zero_delays	8.000s	184.218us	0	1	0.00
V2	mbx_imbx_oob	mbx_imbx_oob	7.000s	209.324us	0	1	0.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	13.000s	1.511ms	1	1	100.00
V2	alert_test	mbx_alert_test	3.000s	39.792us	1	1	100.00
V2	intr_test	mbx_intr_test	3.000s	14.349us	1	1	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	2.000s	39.678us	1	1	100.00
V2	tl_d_illegal_access	mbx_tl_errors	2.000s	39.678us	1	1	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	2.000s	21.842us	1	1	100.00
		mbx_csr_rw	2.000s	79.942us	1	1	100.00
		mbx_csr_aliasing	3.000s	40.435us	1	1	100.00
		mbx_same_csr_outstanding	3.000s	36.874us	1	1	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	2.000s	21.842us	1	1	100.00
		mbx_csr_rw	2.000s	79.942us	1	1	100.00
		mbx_csr_aliasing	3.000s	40.435us	1	1	100.00
		mbx_same_csr_outstanding	3.000s	36.874us	1	1	100.00
V2		TOTAL			5	8	62.50
V2S	tl_intg_err	mbx_tl_intg_err	3.000s	285.246us	1	1	100.00
		mbx_sec_cm	4.000s	17.226us	1	1	100.00
V2S		TOTAL			2	2	100.00
		TOTAL			13	16	81.25

Failure Buckets

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 3 failures:

  • Test mbx_stress has 1 failures.

    • 0.mbx_stress.11655563454989946407612873852677346586620583269974340782800428430871851997622
      Line 101, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log

        UVM_ERROR @ 148649204 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 148649204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test mbx_stress_zero_delays has 1 failures.

    • 0.mbx_stress_zero_delays.83918943574920662043194114940600487226812946689009717441326462087735355358384
      Line 368, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log

        UVM_ERROR @ 184218410 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 184218410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test mbx_imbx_oob has 1 failures.

    • 0.mbx_imbx_oob.83982142964984128407838261662558509814227074876311338353797590996602751063236
      Line 88, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log

        UVM_ERROR @ 209324432 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 209324432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---